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    Auto frequency calibration for a phase locked loop and method of use
    1.
    发明授权
    Auto frequency calibration for a phase locked loop and method of use 有权
    锁相环的自动频率校准和使用方法

    公开(公告)号：US08953730B2

    公开(公告)日：2015-02-10

    申请号：US13452138

    申请日：2012-04-20

    申请人： Yen-Jen Chen ,  Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou

    发明人： Yen-Jen Chen ,  Feng Wei Kuo ,  Huan-Neng Chen ,  Chewn-Pu Jou

    IPC分类号： H03D3/24

    CPC分类号： H03L7/0802 ,  G04F10/005 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/101 ,  H03L7/103 ,  H03L7/104 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M3/32

    摘要： A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal.

    摘要翻译： 锁相环包括被配置为接收参考频率和分频器频率并输出相位差信号的相位差检测器。 锁相环包括被配置为接收参考频率和相位差信号的码发生器，并输出粗调谐信号和复位信号。 锁相环包括配置为接收相位差信号并输出​​微调信号的数字环路滤波器。 锁相环包括配置成接收粗调和微调信号并输出​​输出频率的压控振荡器。 锁相环包括分配器，用于接收复位信号，分频器数控制信号和输出频率，并输出分频器。 锁相环包括被配置为接收除数比和复位信号的delta-sigma调制器，并输出分频数控制信号。

    Noise decoupling structure with through-substrate vias
    2.
    发明授权
    Noise decoupling structure with through-substrate vias 有权
    带通孔的噪声去耦结构

    公开(公告)号：US08928127B2

    公开(公告)日：2015-01-06

    申请号：US12889650

    申请日：2010-09-24

    申请人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Sally Liu

    发明人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Sally Liu

    IPC分类号： H01L23/552 ,  H01L23/58

    CPC分类号： H01L23/66 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/585 ,  H01L29/0619 ,  H01L2223/6616 ,  H01L2223/6666 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate.

    摘要翻译： 一种装置包括具有前表面和后表面的基板; 在基板的前表面上的集成电路器件; 以及在所述基板的背面上的金属板，其中，所述金属板与所述集成电路器件的整体重叠。 保护环延伸到基板中并且环绕集成电路装置。 保护环由导电材料形成。 贯穿基板通孔（TSV）穿透基板并与金属板电耦合。

    Low cost metal-insulator-metal capacitors
    3.
    发明授权
    Low cost metal-insulator-metal capacitors 有权
    低成本的金属 - 绝缘体 - 金属电容器

    公开(公告)号：US08803286B2

    公开(公告)日：2014-08-12

    申请号：US12940523

    申请日：2010-11-05

    申请人： Chewn-Pu Jou ,  Tse-Hua Lu

    发明人： Chewn-Pu Jou ,  Tse-Hua Lu

    IPC分类号： H01L29/92

    CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2224/13

    摘要： A device includes a top metal layer over a substrate; a copper-containing metal feature in the top metal layer; a passivation layer over the top metal layer; and a capacitor. The capacitor includes a bottom electrode including at least a portion in the first passivation layer, wherein the bottom electrode includes aluminum; an insulator over the bottom electrode; and a top electrode over the insulator.

    摘要翻译： 一种器件包括在衬底上的顶部金属层; 顶部金属层中的含铜金属特征; 顶部金属层上的钝化层; 和电容器。 电容器包括底电极，其包括第一钝化层中的至少一部分，其中底电极包括铝; 底部电极上的绝缘体; 和绝缘体上方的顶部电极。

    Up-conversion mixer having a reduced third order harmonic
    6.
    发明授权
    Up-conversion mixer having a reduced third order harmonic 有权
    具有降低的三阶谐波的上变频混频器

    公开(公告)号：US08593206B2

    公开(公告)日：2013-11-26

    申请号：US13084885

    申请日：2011-04-12

    申请人： Huan-Neng Chen ,  Ying-Ta Lu ,  Mei-Show Chen ,  Chewn-Pu Jou

    发明人： Huan-Neng Chen ,  Ying-Ta Lu ,  Mei-Show Chen ,  Chewn-Pu Jou

    IPC分类号： G06F7/44

    CPC分类号： H04L27/06 ,  G06G7/16 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1491 ,  H03D2200/0019 ,  H04L27/04

    摘要： According to some embodiments, an up-conversion mixer includes a mixer cell having an output node arranged to provide an output. An input stage is coupled to the mixer cell and arranged to receive an input signal. The mixer cell is configured to generate the output with an up-converted frequency compared to an input frequency of the input signal. The input stage is configured to reduce a third order harmonic term of the output so that an output power plot of the third order harmonic term with respect to an input power has a notch with a local minimum.

    摘要翻译： 根据一些实施例，上变频混频器包括具有布置成提供输出的输出节点的混频器单元。 输入级耦合到混频器单元并被布置成接收输入信号。 混频器单元被配置为与输入信号的输入频率相比产生具有上转换频率的输出。 输入级被配置为减少输出的三阶谐波项，使得相对于输入功率的三阶谐波项的输出功率图具有局部最小值的陷波。

    AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE
    7.
    发明申请
    AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE 有权
    用于相位锁定环的自动频率校准及其使用方法

    公开(公告)号：US20130278303A1

    公开(公告)日：2013-10-24

    申请号：US13452138

    申请日：2012-04-20

    申请人： Yen-Jen CHEN ,  Feng Wei KUO ,  Huan-Neng CHEN ,  Chewn-Pu JOU

    发明人： Yen-Jen CHEN ,  Feng Wei KUO ,  Huan-Neng CHEN ,  Chewn-Pu JOU

    IPC分类号： H03L7/08 ,  H03L7/00 ,  H03B19/00

    CPC分类号： H03L7/0802 ,  G04F10/005 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/101 ,  H03L7/103 ,  H03L7/104 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M3/32

    摘要： A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal.

    摘要翻译： 锁相环包括被配置为接收参考频率和分频器频率并输出相位差信号的相位差检测器。 锁相环包括被配置为接收参考频率和相位差信号的码发生器，并输出粗调谐信号和复位信号。 锁相环包括配置为接收相位差信号并输出​​微调信号的数字环路滤波器。 锁相环包括配置成接收粗调和微调信号并输出​​输出频率的压控振荡器。 锁相环包括分配器，用于接收复位信号，分频器数控制信号和输出频率，并输出分频器。 锁相环包括被配置为接收除数比和复位信号的delta-sigma调制器，并输出分频数控制信号。

    PHASE FREQUENCY DETECTOR CIRCUIT
    9.
    发明申请
    PHASE FREQUENCY DETECTOR CIRCUIT 有权
    相位检测电路

    公开(公告)号：US20130135011A1

    公开(公告)日：2013-05-30

    申请号：US13308274

    申请日：2011-11-30

    申请人： Yen-Jen CHEN ,  I-Ting LEE ,  Feng Wei KUO ,  Huan-Neng CHEN ,  Chewn-Pu JOU

    发明人： Yen-Jen CHEN ,  I-Ting LEE ,  Feng Wei KUO ,  Huan-Neng CHEN ,  Chewn-Pu JOU

    IPC分类号： H03D13/00 ,  H03L7/00

    CPC分类号： H03D13/00 ,  H03D13/004 ,  H03L7/087 ,  H03L7/089 ,  H03L7/10

    摘要： A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.

    摘要翻译： 相位频率检测器电路包括边缘检测器电路，多个相位频率检测器子电路和判定电路。 边缘检测器电路被配置为接收第一输入信号和第二输入信号。 判定电路被配置为基于边缘检测器电路的输出和多个相位频率检测器子电路的输出来检测盲状态是否退出。 响应于判定电路的结果，多个相位频率检测器子电路的对应的频率检测器子电路被配置为提供用于确定第一输入信号和第二输入信号之间的相位差的信号。

    Linear-cap varactor structures for high-linearity applications
    10.
    发明授权
    Linear-cap varactor structures for high-linearity applications 有权
    线性可变电抗器结构，用于高线性应用

    公开(公告)号：US08373248B2

    公开(公告)日：2013-02-12

    申请号：US12858291

    申请日：2010-08-17

    申请人： Chia-Chung Chen ,  Chewn-Pu Jou

    发明人： Chia-Chung Chen ,  Chewn-Pu Jou

    IPC分类号： H01L29/08

    CPC分类号： H01L29/93 ,  H01L27/0629 ,  H01L27/0808

    摘要： A device includes a well region over a substrate, and a heavily doped well region over the well region, wherein the well region and the heavily doped well region are of a same conductivity type. A gate dielectric is formed on a top surface of the heavily doped well region. A gate electrode is formed over the gate dielectric. A source region and a drain region are formed on opposite sides of the heavily doped well region. The source region and the drain region have bottom surfaces contacting the well region, and wherein the source region and the drain region are of opposite conductivity types.

    摘要翻译： 器件包括衬底上的阱区域以及阱区上的重掺杂阱区，其中阱区和重掺杂阱区具有相同的导电类型。 栅极电介质形成在重掺杂阱区的顶表面上。 在栅极电介质上形成栅电极。 源极区和漏极区形成在重掺杂阱区的相对侧上。 源极区域和漏极区域具有与阱区域接触的底表面，并且其中源极区域和漏极区域具有相反的导电类型。