公开(公告)号：US5877964A

公开(公告)日：1999-03-02

申请号：US781401

申请日：1997-01-10

申请人： Lars Wolfgang Liebmann ,  Robert T. Sayah

发明人： Lars Wolfgang Liebmann ,  Robert T. Sayah

IPC分类号： H01L21/82 ,  G06F17/50 ,  H01L27/02

CPC分类号： H01L27/0207 ,  G06F17/5068

摘要： A method is provided that automatically generates compensated semiconductor devices based on existing VLSI CAD database circuit designs. The preferred method forms a plurality of edge projection shapes which are intersected with active area shapes to form gate edge shapes. The gate edge shapes and residual of the edge shapes are the sorted according to their relative position. These shapes are then selectively biased according to their relative position, and then are used to compensate the existing gate conductor shapes. Thus, this method provides a way to generate gate structures with compensated gate lengths for n-channel and p-channel devices based on existing gate, diffusion and implant designs. This system has the advantage of generating designs with detailed attention to the placement and minimization of jogs that negatively impact the lithography performance.

公开(公告)号：US20130159955A1

公开(公告)日：2013-06-20

申请号：US13328976

申请日：2011-12-16

申请人： Rani Abou Ghaida ,  Kanak Behari Agarwal ,  Lars Wolfgang Liebmann ,  Sani Richard Nassif

发明人： Rani Abou Ghaida ,  Kanak Behari Agarwal ,  Lars Wolfgang Liebmann ,  Sani Richard Nassif

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5081

摘要： A method, system, and computer program product for improving pin access in a design of an integrated circuit (IC) for multi-patterning lithography (MPL) are provided in the illustrative embodiments. A cell is placed in the IC design, the cell including a pin shape configured to connect a pin of the cell to a semi-conductor component in the IC design, the cell including a coloring conflict due to the pin shape and an other shape in the cell each being colored using a first color for fabricating onto a wafer using MPL. A net is routed to the pin shape without resolving the coloring conflict, wherein the routing routes the net using a first segment of the pin shape. The pin shape is modified after routing to resolve the coloring conflict to result in a modified cell.

摘要翻译： 在说明性实施例中提供了用于在用于多图案化光刻（MPL）的集成电路（IC）的设计中改善引脚访问的方法，系统和计算机程序产品。 电池被放置在IC设计中，电池包括被配置为将电池的引脚连接到IC设计中的半导体部件的引脚形状，该电池包括由于引脚形状引起的着色冲突和其他形状 每个单元均使用第一种颜色进行着色，以使用MPL制造到晶片上。 网络被路由到引脚形状而不解决着色冲突，其中，路由使用引脚形状的第一段路由网络。 引脚形状在路由后修改以解决着色冲突，从而导致修改的单元格。

公开(公告)号：US5740068A

公开(公告)日：1998-04-14

申请号：US655790

申请日：1996-05-30

申请人： Lars Wolfgang Liebmann ,  Robert Thomas Sayah ,  John Edward Barth, Jr.

发明人： Lars Wolfgang Liebmann ,  Robert Thomas Sayah ,  John Edward Barth, Jr.

IPC分类号： G03F1/00 ,  G03F1/36 ,  G03F7/20 ,  H01L21/027 ,  G03F7/00 ,  H01J37/304

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： A method for performing optical proximity correction is disclosed that not only limits the optical proximity correction to electrically relevant structures, but also improves the accuracy of the corrections by processing individual feature edges, and minimizes the mask manufacturing impacts by avoiding the introduction of jogs into the design. Critical edge regions of the relevant electrical structures are analyzed, sorted and manipulated to receive optical proximity corrections.

摘要翻译： 公开了一种用于执行光学邻近校正的方法，其不仅将光学邻近校正限制到电气相关结构，而且还通过处理单个特征边缘来提高校正的精度，并且通过避免将点动灯引入到接近校正中来最小化掩模制造影响 设计。 对相关电气结构的临界边缘区域进行分析，分类和操作以接收光学邻近校正。

公开(公告)号：US6055367A

公开(公告)日：2000-04-25

申请号：US250909

申请日：1999-02-16

申请人： Lars Wolfgang Liebmann ,  Robert T. Sayah

发明人： Lars Wolfgang Liebmann ,  Robert T. Sayah

IPC分类号： H01L21/82 ,  G06F17/50 ,  H01L27/02

CPC分类号： H01L27/0207 ,  G06F17/5068

摘要： A method is provided that automatically generates compensated semiconductor devices based on existing VLSI CAD database circuit designs. The preferred method forms a plurality of edge projection shapes which are intersected with active area shapes to form gate edge shapes. The gate edge shapes and residual of the edge shapes are the sorted according to their relative position. These shapes are then selectively biased according to their relative position, and then are used to compensate the existing gate conductor shapes. Thus, this method provides a way to generate gate structures with compensated gate lengths for n-channel and p-channel devices based on existing gate, diffusion and implant designs. This system has the advantage of generating designs with detailed attention to the placement and minimization of jogs that negatively impact the lithography performance.

摘要翻译： 提供了一种基于现有VLSI CAD数据库电路设计自动生成补偿半导体器件的方法。 优选的方法形成多个边缘投影形状，其与有源区域形状相交以形成门边缘形状。 门边缘形状和边缘形状的残差根据其相对位置进行分类。 然后根据它们的相对位置选择性地偏置这些形状，然后用于补偿现有的栅极导体形状。 因此，该方法提供了一种基于现有栅极，扩散和植入物设计为n沟道和p沟道器件生成具有补偿栅极长度的栅极结构的方法。 该系统具有产生设计的优点，其细节关注对光刻性能产生不利影响的慢跑的放置和最小化。

公开(公告)号：US06185727B2

公开(公告)日：2001-02-06

申请号：US08570851

申请日：1995-12-12

申请人： Lars Wolfgang Liebmann

发明人： Lars Wolfgang Liebmann

IPC分类号： G06F1750

CPC分类号： G03F1/30

摘要： A checking routine verifies a phase shifted mask (PSM) design based on fundamental principles of PSM and utilizing only basic shape manipulation functions and Boolean operations found in most computer aided design (CAD) systems. The design verification system checks complete chip designs for the two possible design errors that can cause defective masks by eliminating the phase transition; namely, placing a 180° phase region on both sides of a critical feature or completely omitting the phase region adjacent to certain critical features.

摘要翻译： 检查例程基于PSM的基本原理验证相移掩模（PSM）设计，并且仅使用在大多数计算机辅助设计（CAD）系统中发现的基本形状操纵功能和布尔运算。 设计验证系统通过消除相变来检查可能导致有缺陷的掩模的两种可能的设计错误的完整芯片设计。 即在关键特征的两侧放置180°相位区域，或者完全省略与某些关键特征相邻的相位区域。

公开(公告)号：US5657235A

公开(公告)日：1997-08-12

申请号：US434089

申请日：1995-05-03

申请人： Lars Wolfgang Liebmann ,  Ronald Michael Martino ,  J. Tracy Weed

发明人： Lars Wolfgang Liebmann ,  Ronald Michael Martino ,  J. Tracy Weed

IPC分类号： G03F1/00 ,  G03F1/36 ,  G03F7/20 ,  H01J37/304 ,  H01L21/027

CPC分类号： G03F1/36 ,  G03F7/70441

摘要： Energy levels (dose) are manipulated to modify the resultant photomask representation in a controlled manner such that the final image in the semiconductor device fabrication is close to an ideal image. Feature sizes and shapes are modified by assigning relative mask writer doses rather than physically manipulating feature sizes in layout designs. This approach, based on coding of relative dose information onto the design data, allows continuous scale line width variation for all features without impact to data volume. Two embodiments are described. In the first embodiment, distortion knowledge in the form of a lookup table or convolution function is applied to CAD data which is fractured into numerous designs having specific dose assignments. In the alternative embodiment, distortion knowledge in the form of a lookup table or convolution function is applied to CAD data which generates an attribute file containing hierarchical dose information that is mapped onto the mask data. Both embodiments compensate specific mask feature sizes through dose offsets during the mask exposure process.

摘要翻译： 操作能量水平（剂量）以以受控的方式修改所得到的光掩模表示，使得半导体器件制造中的最终图像接近理想图像。 通过分配相对的掩码写入器剂量而不是在布局设计中物理地操作特征尺寸来修改特征尺寸和形状。 这种基于设计数据上的相对剂量信息编码的方法允许所有功能的连续尺度线宽变化，而不影响数据量。 描述两个实施例。 在第一实施例中，将查找表或卷积函数的形式的失真知识应用于被分解成具有特定剂量分配的许多设计的CAD数据。 在替代实施例中，将查找表或卷积函数形式的失真知识应用于CAD数据，该CAD数据生成包含映射到掩码数据上的分级剂量信息的属性文件。 两个实施例在掩模曝光过程期间通过剂量偏移来补偿特定掩模特征尺寸。