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公开(公告)号：US5452412A
公开(公告)日：1995-09-19
申请号：US109414
申请日：1993-08-19
摘要： A graphics processor including an interface for providing triangle primitives and line primitives representing a graphical image, a line drawer for receiving line primitives and for rendering the line primitives, and a triangle interpolator for receiving the triangle primitives from the interface and for providing line primitives therefrom to the line drawer, wherein the interface includes a register for storing graphics image line primitives and for selectively providing the stored line primitives to the line drawer.
摘要翻译： 一种图形处理器，包括用于提供表示图形图像的三角形图元和线图元的接口，用于接收线图元和用于渲染线图元的线抽屉，以及用于从界面接收三角形图元并用于从其提供线图元的三角形插值器 其中所述接口包括用于存储图形图像线原语的寄存器，并且用于选择性地将所存储的线原语提供给线抽屉。
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公开(公告)号：US5457775A
公开(公告)日：1995-10-10
申请号：US122343
申请日：1993-09-15
CPC分类号： G06T15/80 , G06T15/005
摘要： A graphics processor including an interface for providing triangle primitives representing a graphics image, a triangle interpolator coupled to the interface for interpolating a triangle primitive and serially computing multiple line primitives from the triangle primitive, a line renderer coupled to the triangle interpolator for receiving a line primitive from the triangle interpolator and for providing pixels representing the line primitive while the triangle interpolator is computing another line primitive.
摘要翻译： 包括用于提供表示图形图像的三角形图元的接口的图形处理器，耦合到接口的三角形内插器，用于内插三角形原语，并且从三角形原语串行地计算多个线基元;线渲染器，耦合到三角形插值器，用于接收线 来自三角形内插器的原始图形，并且用于在三角形插值器计算另一行图元时提供表示线原语的像素。
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3.发明授权
公开(公告)号：US5511154A
公开(公告)日：1996-04-23
申请号：US313668
申请日：1994-09-27
CPC分类号： G06T15/005
摘要： A memory apparatus includes a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller for regulating access to that buffer. Also included is a circuit, connected to each buffer controller and the receiving circuit, for accessing one or more of said buffers in response to a first serially stored instruction while, in response to at least one other serially stored instruction, concurrently accessing at least one remaining buffer.
摘要翻译： 存储装置包括用于接收并串行存储多个指令的电路和多个缓冲存储器，每个缓冲存储器包括用于调节对该缓冲器的访问的缓冲器控制器。 还包括连接到每个缓冲器控制器和接收电路的电路，用于响应于第一串行存储的指令访问一个或多个所述缓冲器，而响应于至少一个其他串行存储的指令，同时访问至少一个 剩余缓冲区。
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公开(公告)号：US5420972A
公开(公告)日：1995-05-30
申请号：US614357
申请日：1990-11-15
摘要： A bitblt and line draw parameter calculator for preprocessing address information for a bitblt and line draw sequencer. The sequencer computes individual pixel addresses, controls color interpolation pacing and communicates with the memory hypervisor. By partitioning memory addressing into two tasks a first line or bitblt need only be partially processed prior to starting processing on a second line or bitblt.
摘要翻译： 一个bitblt和line draw参数计算器，用于预处理bitblt和line draw sequencer的地址信息。 定序器计算单个像素地址，控制颜色插值起搏并与内存管理程序进行通信。 通过将内存寻址分为两个任务，第一行或位组只需要在第二行或位组开始处理之前进行部分处理。
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公开(公告)号：US5339394A
公开(公告)日：1994-08-16
申请号：US924357
申请日：1992-07-31
CPC分类号： G06F9/52 , G06F9/3824 , G06F9/3879
摘要： A data processing system is provided that includes a plurality of processors each including a circuit for providing a busy signal. The system also includes a plurality of registers for storing data wherein each register is dedicated to a selected processor or a selected set of processors. A control circuit is provided for receiving the busy signals and prohibiting storage from an external device to the registers dedicated a processor when that processor provides a busy signal.
摘要翻译： 提供了一种数据处理系统，其包括多个处理器，每个处理器包括用于提供忙信号的电路。 该系统还包括用于存储数据的多个寄存器，其中每个寄存器专用于所选择的处理器或所选择的一组处理器。 提供控制电路，用于当该处理器提供忙信号时，接收忙信号并禁止从处理器专用于寄存器的存储器。
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