摘要:
A system, method, and computer program product are provided for processing primitive-specific attributes. A portion of a graphics processor is determined to operate in a fast geometry shader mode and a vertex associated with a set of per-vertex attributes is determined to be a shared vertex. The shared vertex is determined to be a non-provoking vertex corresponding to a first primitive that is associated with a first set of per-primitive attributes and the shared vertex is determined to be a provoking vertex corresponding to a second primitive that is associated with a second set of per-primitive attributes. Only one set of the per-vertex attributes associated with the shared vertex is stored and only one of the second set of per-primitive attributes associated with the second primitive is stored.
摘要:
A system, method, and computer program product are provided for processing primitive-specific attributes. A portion of a graphics processor is determined to operate in a fast geometry shader mode and a vertex associated with a set of per-vertex attributes is determined to be a shared vertex. The shared vertex is determined to be a non-provoking vertex corresponding to a first primitive that is associated with a first set of per-primitive attributes and the shared vertex is determined to be a provoking vertex corresponding to a second primitive that is associated with a second set of per-primitive attributes. Only one set of the per-vertex attributes associated with the shared vertex is stored and only one of the second set of per-primitive attributes associated with the second primitive is stored.
摘要:
A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要:
Structure, apparatus, and method for performing conservative hidden surface removal in a graphics processor. Culling is divided into two steps, a magnitude comparison content addressable memory cull operation (MCCAM Cull), and a subpixel cull operation. The MCCAM Cull discards primitives that are hidden completely by previously processed geometry. The Subpixel Cull takes the remaining primitives (which are partly or entirely visible), and determines the visible fragments. In one embodiment the method of performing hidden surface removal includes: selecting a current primitive comprising a plurality of stamps; comparing stamps to stamps from previously evaluated primitives; selecting a first stamp as a currently potentially visible stamp (CPVS) based on a relationship of depth states of samples in the first stamp with depth states of samples of previously evaluated stamps; comparing the CPVS to a second stamp; discarding the second stamp when no part of the second stamp would affect a final graphics display image based on the stamps that have been evaluated; discarding the CPVS and making the second stamp the CPVS, when the second stamp hides the CPVS; dispatching the CPVS and making the second stamp the CPVS when both the second stamp and the CPVS are at least partially visible in the final graphics display image; and dispatching the second stamp and the CPVS when the visibility of the second stamp and the CPVS depends on parameters evaluated later in the computer graphics pipeline.
摘要:
A 3D graphics accelerator operates in parallel with a host central processing unit (CPU). Software executing on the host CPU performs transformation and lighting operations on 3D-object primitives such as triangles, and generates gradients across the triangle for red, green, blue, Z-depth, alpha, fog, and specular color components. The gradients for texture attributes are also generated and sent to the graphics accelerator. Both the graphics accelerator and the CPU software perform triangle edge and span walking in synchronization to each other. The CPU software walks the triangle to interpolate non-texture color and depth attributes, while the graphics accelerator walks the triangle to interpolate texture attributes. The graphics accelerator performs a non-linear perspective correction and reads a texture pixel from a texture map. The texture pixel is combined with a color pixel that is received from the CPU software interpolation of non-texture attributes. Once the texture pixel from the graphics accelerator and the color pixel from the CPU software are sent to a blender in the graphics accelerator, both continue to interpolate the next pixel in the horizontal-line span, or move to a pixel in the next span. Both the CPU software and the graphics accelerator interpolate the same pixel at the same time. Using both the CPU and the graphics accelerator improves performance since both operate in parallel on the same pixel at the critical interpolation bottleneck.
摘要:
A polygon rendering circuit for a computer color graphics system comprising an edge stepper which steps along edges of an input polygon to determine the span of the polygon along each scan line intersected by the polygon. The coordinate values of the edges on each scan line are determined to sub-pixel resolution such that only those pixels whose centers lie within the true polygon edges (within the span width) must be drawn. Processing efficiency is improved and bandwidth is minimized by passing only those edges of the polygon which are new to that polygon and by computing the Z values in the same manner as, and in parallel with, the X values. Improved results are also possible in accordance with the technique of the invention, for since adjacent polygons compute the same edge by stepping, there can be no gaps between polygons due to round-off errors.
摘要:
A method and apparatus for tiling a display area defined by lines joining vertices with a surface normal vector associated with each vertex whereby the display area is subdivided into sub-display areas by calculating additional vertices and surface normal vectors by interpolation and rendering a given sub-display area by calculating intensity values at its vertices and tiling its area by linear interpolation of the calculated vertex intensity values.
摘要:
A shading circuit has a unit for calculating coordinates and intensities of points inside a polygon based on X, Y, and Z coordinates and intensities of vertexes of each of polygons constituting a solid model. This unit includes a preprocessing section for obtaining the depth change .DELTA.Z/.DELTA.X of Z coordinate for each unit change in X coordinate and the change .DELTA.I/.DELTA.X of intensity for each unit change in X coordinate, based on X, Y, and Z coordinates and intensities of three vertexes of each of triangular polygons constituting a solid model, and a digital differential analyzer until for obtaining Z coordinates and intensities of points inside each polygon commonly using .DELTA.Z/.DELTA.X and .DELTA.I/.DELTA.X when the X and Y coordinates of the points are determined.
摘要翻译:阴影电路具有用于根据构成实体模型的多边形的X,Y和Z坐标和顶点的强度来计算多边形内的点的坐标和强度的单元。 该单元包括一个预处理部分,用于基于X,Y,Y,X坐标的每个单位变化,获得X坐标中每个单位变化的Z坐标的深度变化DELTA Z / DELTA X,以及X坐标的每个单位变化的强度的变化DELTA I / DELTA X, 以及构成实体模型的每个三角形多边形的三个顶点的Z坐标和强度,以及数字差分分析仪,直到当通过使用DELTA Z / DELTA X和DELTA I / DELTA X来获得每个多边形内的点的Z坐标和强度时 确定点的X和Y坐标。
摘要:
A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要:
In order to render a primitive, the primitive is subdivided into trapezoids and triangles. The subdivision occurs using scanline-aligned lines. These simple scanline-aligned regions are further subdivided so that the primitive is divided into simple scanline-boundaried trapezoids and other complex scan shapes. The simple scanline-boundaried trapezoids are rasterized. One rasterization method uses a texture map containing slope-based coverage information to edge areas. Gouraud shading may be used to provide the anti-aliasing effects on the scanline-boundaried trapezoids. The simple scanline-boundaried trapezoids may also be rasterized using a software rasterizer. Complex scans are rasterized using a software rasterizer. As data is already rasterized, it is thereby efficiently transferred to the GPU.