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14 条记录 (耗时 0.023 秒)

    Aiding in a satellite positioning system
    3.
    发明授权
    Aiding in a satellite positioning system 有权
    协助卫星定位系统

    公开(公告)号：US07236883B2

    公开(公告)日：2007-06-26

    申请号：US10515808

    申请日：2003-12-04

    申请人： Lionel Jacques Garin ,  Leon Kuo-Liang Peng ,  Gengsheng Zhang ,  Nicolas Patrick Vantalon

    发明人： Lionel Jacques Garin ,  Leon Kuo-Liang Peng ,  Gengsheng Zhang ,  Nicolas Patrick Vantalon

    IPC分类号： G01C21/00

    CPC分类号： G01S19/256 ,  G01S19/235 ,  G01S19/254

    摘要： The invention relates to an aided Global Positioning System (GPS) subsystem within a wireless device. The wireless device includes a wireless processing section capable of receiving signals from a wireless network and a GPS subsystem having a radio frequency (RF) front-end capable of receiving a GPS satellite signal. The wireless processing section of the wireless device receives an external clock and determines the offset between the clock in the wireless processing section and that of the external clock. The GPS subsystem then receives the offset information from the wireless processing section, information related to the nominal frequency of the wireless processing section clock and the wireless processing section clock. Using this information and the GPS clock in the GPS subsystem, the GPS subsystem determines an acquiring signal, which is related to a frequency offset between the GPS clock and the network clock. The GPS subsystem then acquires GPS satellite signals in an acquiring unit though the use of the acquiring signal.

    摘要翻译： 本发明涉及无线设备内的辅助全球定位系统（GPS）子系统。 无线设备包括能够从无线网络接收信号的无线处理部分和具有能够接收GPS卫星信号的射频（RF）前端的GPS子系统。 无线装置的无线处理部接收外部时钟并确定无线处理部中的时钟与外部时钟的时钟之间的偏移。 然后，GPS子系统接收来自无线处理部分的偏移信息，与无线处理部分时钟的标称频率和无线处理部分时钟有关的信息。 在GPS子系统中使用该信息和GPS时钟，GPS子系统确定与GPS时钟和网络时钟之间的频率偏移相关的获取信号。 然后，GPS子系统通过使用采集信号在获取单元中获取GPS卫星信号。

    Tracker architecture for GPS systems
    4.
    发明授权
    Tracker architecture for GPS systems 有权
    GPS系统的跟踪器架构

    公开(公告)号：US07091904B2

    公开(公告)日：2006-08-15

    申请号：US10199253

    申请日：2002-07-18

    申请人： Nicolas Vantalon ,  Leon Kuo-Liang Peng ,  Gregory Turetzky

    发明人： Nicolas Vantalon ,  Leon Kuo-Liang Peng ,  Gregory Turetzky

    IPC分类号： G01S5/14 ,  G06F15/163

    CPC分类号： G01S19/37 ,  G01S19/34 ,  G01S19/35 ,  G01S19/46

    摘要： A tracker architecture for Global Positioning System (GPS) receivers is disclosed. A typical tracker comprises an RF front end and GPS architecture. The architecture comprises a bus structure, a Central Processing Unit (CPU) core, cache, RAM, and ROM memories, and a GPS engine that comprises a receiving, tracking, and demodulating engine for GPS and Wide Area Augmentation Service (WAAS) signals. The GPS architecture can couple to at least two different protocol interfaces via the bus structure, where the protocol interfaces are commonly used in different applications.

    摘要翻译： 公开了全球定位系统（GPS）接收机的跟踪架构。 典型的跟踪器包括RF前端和GPS架构。 该架构包括总线结构，中央处理单元（CPU）核心，高速缓存，RAM和ROM存储器，以及包括用于GPS和广域增强服务（WAAS）信号的接收，跟踪和解调引擎的GPS引擎。 GPS架构可以通过总线结构耦合到至少两个不同的协议接口，其中协议接口通常用于不同的应用。

    Shared memory architecture in GPS signal processing
    5.
    发明授权
    Shared memory architecture in GPS signal processing 有权

    公开(公告)号：US06930634B2

    公开(公告)日：2005-08-16

    申请号：US10309647

    申请日：2002-12-04

    申请人： Leon Kuo-Liang Peng ,  Henry D. Falk

    发明人： Leon Kuo-Liang Peng ,  Henry D. Falk

    IPC分类号： G01S1/00 ,  G06F12/00

    CPC分类号： G01S19/24 ,  G01S19/29 ,  G01S19/37

    摘要： A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

    Autonomous hardwired tracking loop coprocessor for GPS and WAAS receiver
    6.
    发明授权
    Autonomous hardwired tracking loop coprocessor for GPS and WAAS receiver 有权

    公开(公告)号：US06278403B1

    公开(公告)日：2001-08-21

    申请号：US09397438

    申请日：1999-09-17

    申请人： Leon Kuo-Liang Peng ,  Henry D. Falk ,  Wesley F. Marumo

    发明人： Leon Kuo-Liang Peng ,  Henry D. Falk ,  Wesley F. Marumo

    IPC分类号： G01S502

    CPC分类号： G01S19/37 ,  G01S19/29 ,  G01S19/30 ,  G01S19/34 ,  H04L27/2273

    摘要： An autonomous Hardwired Tracking Loop (HWTL) ASIC comprising a HWTL coprocessor provided for implementing most of the receiver processing function for data acquisition and tracking functions of a radio receiver system in dedicated hardware. With the expanded functionality provided by an HWTL coprocessor in the autonomous HWTL ASIC, the interruption of CPU performing the navigation processing is significantly reduced to thereby maximize throughput and minimize power burden on the microprocessor. In the preferred embodiment, the HWTL ASIC also comprises the CPU and a correlator, wherein the correlator provides the high rate greater than approximately 1 KHz signal processing operations, the HWTL coprocessor providing the data acquisition and tracking (medium frequency signal processing) operations, and the CPU thereby freed to provide more bandwidth for lower frequency processing, i.e., navigation and non-radio receiver operations, such as user applications, processing requiring CPU intervention at approximately 10 Hz or less CPU processing rate.

    Shared memory architecture in GPS signal processing
    9.
    发明授权
    Shared memory architecture in GPS signal processing 有权

    公开(公告)号：US06526322B1

    公开(公告)日：2003-02-25

    申请号：US09465985

    申请日：1999-12-16

    申请人： Leon Kuo-Liang Peng ,  Henry D. Falk

    发明人： Leon Kuo-Liang Peng ,  Henry D. Falk

    IPC分类号： G05B1942

    CPC分类号： G01S19/24 ,  G01S19/29 ,  G01S19/37

    摘要： A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

    Lookaside buffer for address translation in a computer system
    10.
    发明授权
    Lookaside buffer for address translation in a computer system 失效
    用于计算机系统中地址转换的后备缓冲区

    公开(公告)号：US5893931A

    公开(公告)日：1999-04-13

    申请号：US783967

    申请日：1997-01-15

    申请人： Leon Kuo-Liang Peng ,  Yolin Lih ,  Chih-Wei David Chang

    发明人： Leon Kuo-Liang Peng ,  Yolin Lih ,  Chih-Wei David Chang

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F12/1009

    摘要： A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (TLB) and, possibly, a translation table held in memory and implemented as a B-tree data structure. The TLB is initially searched for a translation for a specified input address. If exactly one valid entry of the TLB stores a translation for the specified input address then the output address corresponding to the specified input address is determined from the contents of that entry. Otherwise, the translation table is searched for a translation for the specified input address. If two or more valid entries of the TLB store a translation for the specified input address then these entries are invalidated. If a search of the translation table is required then the method involves the retrieval from the translation table, and insertion into the TLB, of a translation for the specified input address and possibly one or more translations for other input addresses that are stored together with the translation for the specified input address in one node of the B-tree implementing the translation table. During the insertion into the TLB of a translation for a particular input address that was retrieved from the translation table it is determined if there is exactly one valid entry in the TLB that stores a translation for the particular input address. If so, then the translation retrieved from the memory is inserted into that entry, thereby avoiding the creation of multiple TLB entries for the same input address.

    摘要翻译： 一种用于在支持虚拟存储器的计算机系统中执行地址转换的方法和装置，该方法和装置通过搜索保存在存储器中并实现为B树数据结构的翻译后备缓冲器（TLB）和可能的翻译表来实现。 TLB最初是搜索指定输入地址的翻译。 如果TLB的一个有效条目存储了指定输入地址的转换，则根据该条目的内容确定与指定输入地址对应的输出地址。 否则，翻译表被搜索用于指定输入地址的翻译。 如果TLB的两个或多个有效条目存储指定输入地址的转换，则这些条目无效。 如果需要对翻译表的搜索，则该方法涉及从转换表中检索并插入到TLB中的用于指定输入地址的翻译，以及可能与其中一起存储的其它输入地址的一个或多个翻译 在实现翻译表的B树的一个节点中为指定的输入地址进行翻译。 在从转换表中检索到的特定输入地址的翻译插入到TLB期间，确定TLB中是否存在恰好一个存储特定输入地址的转换的有效条目。 如果是这样，则将从存储器检索的翻译插入到该条目中，从而避免为相同的输入地址创建多个TLB条目。