公开(公告)号：US07076415B1

公开(公告)日：2006-07-11

申请号：US09560844

申请日：2000-04-28

申请人： Michael J. Demler ,  Stephen Lim ,  Geoffrey Ellis ,  Leslie D. Spruiell ,  Robert W. McGuffin ,  Bent H. Sorensen

发明人： Michael J. Demler ,  Stephen Lim ,  Geoffrey Ellis ,  Leslie D. Spruiell ,  Robert W. McGuffin ,  Bent H. Sorensen

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5054 ,  G06F2217/86

摘要： Circuit synthesis is performed utilizing an optimizer that selects design parameters for a synthesis model of a circuit based on desired performance characteristics and performance characteristics/design parameters of previously synthesized circuits. Performance characteristics and design parameters of each synthesized circuit are maintain in conjunction with the synthesis model of the circuit being synthesized. A synthesis plan identifies the synthesis model and specific instructions on how to perform optimized selection of design parameters, how to set up test benches, and how to perform the simulation.

摘要翻译： 利用优化器进行电路合成，所述优化器基于期望的性能特征和先前合成的电路的性能特征/设计参数来选择电路的合成模型的设计参数。 每个合成电路的性能特征和设计参数与正在合成的电路的合成模型相结合。 综合计划确定了如何执行设计参数优化选择，如何设置测试台以及如何执行仿真的综合模型和具体说明。

公开(公告)号：US06356796B1

公开(公告)日：2002-03-12

申请号：US09216752

申请日：1998-12-17

申请人： Leslie D. Spruiell ,  Robert W. McGuffin ,  Bendt H. Sorensen ,  Michael J. Demler

发明人： Leslie D. Spruiell ,  Robert W. McGuffin ,  Bendt H. Sorensen ,  Michael J. Demler

IPC分类号： G06F1900

CPC分类号： G06F17/5063 ,  G06F17/5036 ,  G06F17/5045

摘要： A Language Controlled Design Flow for the development of integrated circuits (IC) that allows users to Characterize, Synthesize, Simulate, and Analyze IC designs. The Language Controlled Design Flow provides specialized features that enable rapid design development and Intellectual Property (IP) reuse. The language provides the ability to capture a designer's knowledge about the Design Components and Design Processes unique to those components during characterization, synthesis, simulation, and analysis. A feature of this invention is the ability to separate design or design component specific knowledge from the tools used for analysis. This leads to benefits in extensibility, simplicity, accuracy, and performance of the overall tool set. Also provided is a mechanism in which the design process can be fully automated with a Language Controlled Design Flow that can take advantage of the information available in the design, in the design components, and in the design process flow. Additionally, this invention may be implemented in a set of commercially available computer software programs.

摘要翻译： 用于开发集成电路（IC）的语言控制设计流程，允许用户对IC设计进行特征，合成，模拟和分析。 语言控制设计流程提供了专门的功能，可实现快速设计开发和知识产权（IP）重用。 该语言提供了在表征，综合，仿真和分析期间捕获设计人员对这些组件特有的设计组件和设计过程的了解。 本发明的一个特征是能够将组件特定知识与用于分析的工具分开设计或设计。 这将导致整体工具集的可扩展性，简单性，准确性和性能的好处。 还提供了一种机制，其中设计过程可以通过语言控制的设计流程完全自动化，该流程可以利用设计，设计组件以及设计过程流程中可用的信息。 另外，本发明可以在一组市售的计算机软件程序中实现。

公开(公告)号：US07191112B2

公开(公告)日：2007-03-13

申请号：US09843573

申请日：2001-04-26

申请人： Michael J. Demler ,  Stephen Lim ,  Geoffrey Ellis

发明人： Michael J. Demler ,  Stephen Lim ,  Geoffrey Ellis

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5063 ,  G06F17/5036

摘要： Test benches, simulations, and scripts are invoked in parallel for testing multiple points in a circuit being synthesized in an Analog Mixed Signal environment. A simulation system for simultaneously optimizing performance characteristics in circuit synthesis uses a set of design parameters. At least one circuit model is used to incorporate the set of design parameters, each circuit model adapted to model a portion of the circuit pertaining to a performance characteristic. At least one analysis test bench is then connected to each circuit model. Each analysis test bench is adapted to model circuitry external to the circuit and control the type of analysis to be performed for each performance characteristic of the circuit.

摘要翻译： 测试台，仿真和脚本被并行调用，用于测试在模拟混合信号环境中合成的电路中的多个点。 用于同时优化电路合成中的性能特征的仿真系统使用一组设计参数。 使用至少一个电路模型来结合该组设计参数，每个电路模型适于对与性能特征相关的电路的一部分进行建模。 至少有一个分析测试台连接到每个电路模型。 每个分析测试台适用于对电路外部的电路进行建模，并控制要为电路的每个性能特性执行的分析类型。

公开(公告)号：US06813597B1

公开(公告)日：2004-11-02

申请号：US09589966

申请日：2000-06-08

申请人： Michael J. Demler

发明人： Michael J. Demler

IPC分类号： G06F1750

CPC分类号： G06F17/5036 ,  G06F17/5063

摘要： Method and apparatus for the synthesis of electronic circuits and, more particuarly, to the synthesis of analog circuitry and mixed digital and analog circuitry, and related to the reuse of circuit designer knowledge for the simulation of mixed analog and digital circuitry to determine data points and to curve fit the data points to determine a polynomial equation that closely approximates simulated circuit performance, and related to the parameterization of circuit features with respect to circuit performance.

摘要翻译： 用于合成电子电路的方法和装置，更具体地说，涉及模拟电路和混合数字和模拟电路的合成，并且涉及电路设计者知识的重用以用于模拟混合模拟和数字电路以确定数据点和 曲线拟合数据点，以确定近似于模拟电路性能的多项式方程，并且与电路特性相关于电路性能的参数化相关。

公开(公告)号：US5148054A

公开(公告)日：1992-09-15

申请号：US741549

申请日：1991-08-07

申请人： Michael J. Demler

发明人： Michael J. Demler

IPC分类号： H03K5/24 ,  H03K17/16 ,  H03K17/693

CPC分类号： H03K17/693 ,  H03K17/162 ,  H03K5/249

摘要： A high-accuracy MOSFET-switched sampling circuit feeds charge feedthrough error to a load as well as to a dummy load during DC input signal sampling by a switching MOSFET, thereby reducing storage of the charge feedthrough error on the load to the extent that the charge feedthrough error is rather stored on the dummy load. During AC input signal sampling, the high-accuracy MOSFET-switched sampling circuit isolates the AC input signal from the dummy load. Charge feedthrough error produced by an isolating MOSFET that isolates the AC input signal from the dummy load is exactly compensated by a phase-opposed compensating MOSFET positioned in the DC input signal path. The dummy load and the load may be active as well as passive and may be selected to have equal and unequal electrical characteristics. The compensating current produced by the compensating MOSFET may be selected not only to exactly compensate the charge feedthrough error of the isolating MOSFET but also to compensate the charge feedthrough error of the switching MOSFET in the DC input signal path. High sampling accuracies are achieved by the instant invention in a wide variety of applications including an exemplary auto-zeroed CMOS comparator.

摘要翻译： 高精度MOSFET开关采样电路通过开关MOSFET在DC输入信号采样期间向负载以及虚拟负载馈送电荷馈通误差，从而减少负载上的电荷馈通误差的存储，使得电荷 馈通错误被存储在虚拟负载上。 在交流输入信号采样期间，高精度MOSFET开关采样电路将交流输入信号与虚拟负载隔离。 通过隔离MOSFET产生的充电馈通误差，隔离MOSFET将交流输入信号与虚拟负载隔离，由位于直流输入信号路径中的相对对置补偿MOSFET精确补偿。 虚拟负载和负载可以是有源的和无源的，并且可以被选择为具有相等和不相等的电特性。 补偿MOSFET产生的补偿电流不仅可以选择精确补偿隔离MOSFET的电荷馈通误差，还可以补偿直流输入信号路径中开关MOSFET的电荷馈通误差。 本发明在各种应用中实现了高采样精度，包括示例性自动归零CMOS比较器。

公开(公告)号：US4539495A

公开(公告)日：1985-09-03

申请号：US613480

申请日：1984-05-24

申请人： Michael J. Demler

发明人： Michael J. Demler

IPC分类号： G01R19/165 ,  G01R19/00 ,  G11C7/06 ,  G11C11/419 ,  H03K3/0233 ,  H03K3/356 ,  H03K5/08 ,  H03K5/24 ,  H03K3/023

CPC分类号： G01R19/0038 ,  G11C7/065 ,  H03K3/35606 ,  H03K3/356095 ,  H03K3/356156 ,  H03K5/249

摘要： The voltage comparator includes a first and a second voltage supply terminal, and a first and a second output node. A first current source is connected between the first supply terminal and the first output node. A first field effect transistor of one channel conductivity type is connected between the first output node and the second supply terminal. The gate of the first transistor is connected to the second output node. A second current source is connected between the first supply terminal and the second output node. A second field effect transistor of the one conductivity is connected between the second output node and the second supply terminal. The gate of the second transistor is connected to the first output node. During a first period of time the first and second output nodes and the capacitances of the gates of the first and second transistors connected thereto are maintained at the potential of the second supply terminal by switches connected thereacross. At the end of the first period the switches are opened allowing the first and second output nodes to charge. Simultaneously charge proportional to a first signal voltage is supplied to the first output node and charge proportional to a second signal voltage is supplied to the second output node. The node which receives the greater charge rapidly charges toward the voltage of the first supply terminal and the node which receives the smaller charge is maintained at the potential of the second supply terminal. Thus, an indication is obtained of the greater of the two voltages.

摘要翻译： 电压比较器包括第一和第二电压供给端子以及第一和第二输出节点。 第一电流源连接在第一电源端子和第一输出节点之间。 一个沟道导电类型的第一场效应晶体管被连接在第一输出节点和第二供电端之间。 第一晶体管的栅极连接到第二输出节点。 第二电流源连接在第一电源端子和第二输出节点之间。 一个电导率的第二场效应晶体管连接在第二输出节点和第二电源端子之间。 第二晶体管的栅极连接到第一输出节点。 在第一时间段期间，连接到第一和第二输出节点的第一和第二晶体管的栅极的电容通过连接在其上的开关保持在第二电源端子的电位。 在第一周期结束时，开关被打开，允许第一和第二输出节点充电。 与第一信号电压成比例的同时充电被提供给第一输出节点，并且与第二信号电压成正比的电荷被提供给第二输出节点。 接收较大电荷的节点向第一电源端子的电压快速充电，并且接收较小电荷的节点保持在第二电源端子的电位。 因此，获得两个电压中较大者的指示。

公开(公告)号：US06637018B1

公开(公告)日：2003-10-21

申请号：US09697064

申请日：2000-10-26

申请人： Michael J. Demler

发明人： Michael J. Demler

IPC分类号： G06F1750

CPC分类号： G06F17/5063

摘要： A method and apparatus for the synthesis of electronic circuits is described herein. More particularly, the system supports the synthesis of both analog-only, and mixed digital/analog circuitry. The circuit designers knowledge is reused to effect the simulation of mixed analog and digital circuitry, determining data points and curve-fitting the data points to determine a model that closely approximates the simulated circuit performance. The model describes the parameterization of circuit features with respect to circuit performance. The parameterization is used to develop a behavioral model of the circuit that does not retain any of the physical description of the circuit.

摘要翻译： 本文描述了用于合成电子电路的方法和装置。 更具体地，该系统支持仅模拟和混合数字/模拟电路的合成。 电路设计人员的知识被重新用于影响混合模拟和数字电路的仿真，确定数据点并对数据点进行曲线拟合，以确定逼近仿真电路性能的模型。 该模型描述了关于电路性能的电路特征的参数化。 参数化用于开发不保留电路的任何物理描述的电路的行为模型。

公开(公告)号：US5262685A

公开(公告)日：1993-11-16

申请号：US778350

申请日：1991-10-16

申请人： Michael J. Demler ,  Kevin J. McCall

发明人： Michael J. Demler ,  Kevin J. McCall

IPC分类号： G11C27/02 ,  H03K5/24

CPC分类号： G11C27/026 ,  H03K5/249

摘要： Auto-zeroing clocking signals, a first auto-zeroing clocking signal of comparatively-low frequency and duty cycle and a second auto-zeroing clocking signal of the same comparatively-low frequency but complementary and comparatively-high duty cycle, and a sampling clocking signal of comparatively-high frequency respectively initiate auto-zeroing of a circuit element subject to output offset error and data sampling of an A.C. input signal to a latch. The sampling of the A.C. input signal to the latch occurs at the comparatively-high frequency of the clocking signal during the "on" time of the comparatively-high duty cycle second auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide higher speed sampling than heretofore possible. The auto-zeroing of the circuit element subject to input offset error occurs during the "on" time of the comparatively-low duty cycle first auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide lower power sampling than heretofore possible. Typically, the circuit element is either an analog comparator or an operational amplifier, and the sampling circuit of the invention has exemplary utility in analog-to-digital (A/D) conversion.

摘要翻译： 自动归零时钟信号，具有相对较低频率和占空比的第一自动归零时钟信号和具有相同较低频率但互补且相对较高占空比的相同低自适应时钟信号，以及采样时钟信号 相对高的频率分别启动电路元件的自动归零，该电路元件受到输出偏移误差的影响，并将AC输入信号的数据采样到锁存器。 在较低频率的比较高占空比的第二自动归零时钟信号的“接通”时间内，对锁存器的AC输入信号的采样发生在时钟信号的较高频率处，从而能够提供更高的 速度采样比以前可能。 受到输入偏移误差的电路元件的自动归零发生在相对低频率的相对低的占空比第一自动归零时钟信号的“导通”时间，从而能够提供比以前更低的功率采样。 通常，电路元件是模拟比较器或运算放大器，并且本发明的采样电路在模数（A / D）转换中具有示例性的用途。