公开(公告)号：US09311075B2

公开(公告)日：2016-04-12

申请号：US13671569

申请日：2012-11-08

Applicant: Chih-Wei Hu ,  Lin-Hung Chen

Inventor： Chih-Wei Hu ,  Lin-Hung Chen

IPC: G06F9/00 ,  G06F9/445

CPC classification number: G06F8/656

Abstract: An electronic apparatus including a central processing unit (CPU), a chipset, a first interface circuit, a temporary memory, a BIOS (basic input/output system) memory, a second interface circuit and a first switcher is provided. The chipset is coupled to the CPU and the first switcher. The temporary memory is coupled to the first switcher and the first interface circuit. The first interface circuit is coupled to the electronic apparatus and an extended storage including a first BIOS. The second interface circuit is coupled to the first switcher and the BIOS memory. If the first BIOS is stored in the temporary memory, the temporary memory is coupled to the chipset by the first switcher; if the first BIOS is not stored in the temporary memory, the second interface circuit is coupled to the chipset by the first switcher. The electronic device can safely updates the BIOS.

Abstract translation: 提供了包括中央处理单元（CPU），芯片组，第一接口电路，临时存储器，BIOS（基本输入/输出系统）存储器，第二接口电路和第一切换器的电子设备。 该芯片组耦合到CPU和第一个切换台。 临时存储器耦合到第一切换器和第一接口电路。 第一接口电路耦合到电子设备和包括第一BIOS的扩展存储器。 第二接口电路耦合到第一切换器和BIOS存储器。 如果第一BIOS存储在临时存储器中，则临时存储器通过第一切换器耦合到芯片组; 如果第一BIOS不存储在临时存储器中，则第二接口电路通过第一切换器耦合到芯片组。 电子设备可以安全地更新BIOS。

公开(公告)号：US20130159692A1

公开(公告)日：2013-06-20

申请号：US13671569

申请日：2012-11-08

Applicant: Chih-Wei Hu ,  Lin-Hung Chen

Inventor： Chih-Wei Hu ,  Lin-Hung Chen

IPC: G06F9/00

CPC classification number: G06F8/656

Abstract: An electronic apparatus including a central processing unit (CPU), a chipset, a first interface circuit, a temporary memory, a BIOS (basic input/output system) memory, a second interface circuit and a first switcher is provided. The chipset is coupled to the CPU and the first switcher. The temporary memory is coupled to the first switcher and the first interface circuit. The first interface circuit is coupled to the electronic apparatus and an extended storage including a first BIOS. The second interface circuit is coupled to the first switcher and the BIOS memory. If the first BIOS is stored in the temporary memory, the temporary memory is coupled to the chipset by the first switcher; if the first BIOS is not stored in the temporary memory, the second interface circuit is coupled to the chipset by the first switcher. The electronic device can safely updates the BIOS.

Abstract translation: 提供了包括中央处理单元（CPU），芯片组，第一接口电路，临时存储器，BIOS（基本输入/输出系统）存储器，第二接口电路和第一切换器的电子设备。 该芯片组耦合到CPU和第一个切换台。 临时存储器耦合到第一切换器和第一接口电路。 第一接口电路耦合到电子设备和包括第一BIOS的扩展存储器。 第二接口电路耦合到第一切换器和BIOS存储器。 如果第一BIOS存储在临时存储器中，则临时存储器通过第一切换器耦合到芯片组; 如果第一BIOS不存储在临时存储器中，则第二接口电路通过第一切换器耦合到芯片组。 电子设备可以安全地更新BIOS。

公开(公告)号：US20080222409A1

公开(公告)日：2008-09-11

申请号：US12000591

申请日：2007-12-14

Applicant: Chien-Ping Chung ,  Lin-Hung Chen

Inventor： Chien-Ping Chung ,  Lin-Hung Chen

IPC: G06F12/02 ,  G06F15/177

CPC classification number: G06F12/0223 ,  G06F9/4403 ,  G06F12/0284 ,  G06F2212/2022

Abstract: A memory access system for accessing a basic input output system (BIOS) program is provided. The memory access system includes a flash memory, a CPU, a peripheral component interconnect (PCI) slave, an address converter and a flash memory controller. The flash memory stores a number of BIOS data of the BIOS program, and each BIOS data corresponds to a default BIOS address and is allocated in a flash memory type BIOS address. The CPU delivers a BIOS access instruction. The BIOS access instruction corresponds to a default target address of the default BIOS addresses. After the PCI slave interprets the BIOS access instruction, the address converter converts the default target address into a flash memory type target address, which is one of the flash memory type BIOS address. The flash memory controller accesses the BIOS data allocated at the flash memory type target address accordingly.

Abstract translation: 提供了用于访问基本输入输出系统（BIOS）程序的存储器访问系统。 存储器访问系统包括闪存，CPU，外围组件互连（PCI）从站，地址转换器和闪存控制器。 闪存存储BIOS程序的多个BIOS数据，并且每个BIOS数据对应于默认BIOS地址，并且被分配在闪速存储器类型的BIOS地址中。 CPU提供BIOS访问指令。 BIOS访问指令对应于默认的BIOS地址的默认目标地址。 在PCI从站解读BIOS访问指令后，地址转换器将默认目标地址转换为Flash存储器类型的BIOS地址之一的闪存类型目标地址。 闪存控制器相应地访问在闪存类型目标地址处分配的BIOS数据。

公开(公告)号：US07080282B2

公开(公告)日：2006-07-18

申请号：US10063772

申请日：2002-05-11

Applicant: Tsung-Yi Lin ,  Chia-Hsing Yu ,  Lin-Hung Chen

Inventor： Tsung-Yi Lin ,  Chia-Hsing Yu ,  Lin-Hung Chen

IPC: G06F11/00

CPC classification number: G06F11/24 ,  G01R31/3004

Abstract: A method for determining an operating voltage of floating point error detection is implemented by a central processing unit (CPU) and a south bridge chipset. The CPU has a first output port connected to a test port of the south bridge. The test port is used to determine an operating voltage of the CPU. If the operating voltage of the CPU is greater than a predetermined value, the first output port is floating. If the operating voltage of the CPU is smaller than the predetermined value, the first output port is grounded. The method includes using a power supply and a resistor to provide a bias voltage and for measuring a voltage of the test port to determine the operating voltage of the CPU.

公开(公告)号：US20080235428A1

公开(公告)日：2008-09-25

申请号：US11759360

申请日：2007-06-07

Applicant: Chia-Hsing Yu ,  Lin-Hung Chen

Inventor： Chia-Hsing Yu ,  Lin-Hung Chen

IPC: G06F13/36

CPC classification number: G06F13/405

Abstract: A bridge is disclosed. The bridge comprises a first interface having at least one multiplexed clock signal line. The multiplexed clock signal line outputs first and second control signals for respectively controlling the access to first and second devices coupled to the bridge. The bridge selectively outputs the first clock signal or the second clock signal to the multiplexed clock signal line to access the first device or the second device respectively.

Abstract translation: 披露了一座桥梁。 该桥包括具有至少一个复用的时钟信号线的第一接口。 复用的时钟信号线输出第一和第二控制信号，用于分别控制对耦合到桥的第一和第二设备的访问。 桥接器选择性地将第一时钟信号或第二时钟信号输出到复用的时钟信号线以分别访问第一设备或第二设备。

公开(公告)号：US07353315B2

公开(公告)日：2008-04-01

申请号：US11325906

申请日：2006-01-05

Applicant: Lin-Hung Chen ,  Jui-Ming Wei

Inventor： Lin-Hung Chen ,  Jui-Ming Wei

IPC: G06F13/00

CPC classification number: G06F13/385

Abstract: A bus controller and a control method are used in a computer system. In a bus controller, a bus controller main circuit issues a first signal to the central processing unit in response to a bus configuration cycle for indicating the presence of a first-level bus that the first group of components is coupled to. A virtual bridge device issues a second signal to the central processing unit in response to the bus configuration cycle for indicating the presence of a second-level bus that the second group of components is coupled to. A path selection unit electrically connected to the first and second groups of components via the first-level and second-level buses, respectively, outputs a normal device select signal to one of the first-level and second-level buses while outputting an invalid device select signal to the other of the first-level and second-level buses according to address data of a transaction.

Abstract translation: 在计算机系统中使用总线控制器和控制方法。 在总线控制器中，总线控制器主电路响应于用于指示第一组组件耦合到的第一级总线的存在的总线配置周期向中央处理单元发出第一信号。 虚拟桥接设备响应于总线配置周期向中央处理单元发出第二信号，以指示第二组组件耦合到的二级总线的存在。 经由第一级和第二级总线电连接到第一和第二组分组的路径选择单元将正常的设备选择信号输出到第一级总线和第二级总线之一，同时输出无效设备 根据交易的地址数据将信号选择到另一个第一级和第二级总线。

公开(公告)号：US07991990B2

公开(公告)日：2011-08-02

申请号：US12000591

申请日：2007-12-14

Applicant: Chien-Ping Chung ,  Lin-Hung Chen

Inventor： Chien-Ping Chung ,  Lin-Hung Chen

IPC: G06F9/24 ,  G06F9/00 ,  G06F13/00 ,  G06F9/26 ,  G06F9/34

CPC classification number: G06F12/0223 ,  G06F9/4403 ,  G06F12/0284 ,  G06F2212/2022

Abstract: A memory access system for accessing a basic input output system (BIOS) program is provided. The memory access system includes a flash memory, a CPU, a peripheral component interconnect (PCI) slave, an address converter and a flash memory controller. The flash memory stores a number of BIOS data of the BIOS program, and each BIOS data corresponds to a default BIOS address and is allocated in a flash memory type BIOS address. The CPU delivers a BIOS access instruction. The BIOS access instruction corresponds to a default target address of the default BIOS addresses. After the PCI slave interprets the BIOS access instruction, the address converter converts the default target address into a flash memory type target address, which is one of the flash memory type BIOS address. The flash memory controller accesses the BIOS data allocated at the flash memory type target address accordingly.

Abstract translation: 提供了用于访问基本输入输出系统（BIOS）程序的存储器访问系统。 存储器访问系统包括闪存，CPU，外围组件互连（PCI）从站，地址转换器和闪存控制器。 闪存存储BIOS程序的多个BIOS数据，并且每个BIOS数据对应于默认BIOS地址，并且被分配在闪速存储器类型的BIOS地址中。 CPU提供BIOS访问指令。 BIOS访问指令对应于默认的BIOS地址的默认目标地址。 在PCI从站解读BIOS访问指令后，地址转换器将默认目标地址转换为Flash存储器类型的BIOS地址之一的闪存类型目标地址。 闪存控制器相应地访问在闪存类型目标地址处分配的BIOS数据。

公开(公告)号：US07062593B2

公开(公告)日：2006-06-13

申请号：US10098550

申请日：2002-03-18

Applicant: Lin-Hung Chen

Inventor： Lin-Hung Chen

IPC: G06F13/36

CPC classification number: G06F13/4226 ,  G06F13/4269

Abstract: The present invention provides a circuit system for data transmission between LPC devices, comprising: a first LPC bus, connected to a first LPC device; a second LPC bus, connected to a second LPC device; and an LPC host controller, able to drive the first LPC device through the first LPC bus and the second LPC device through the second LPC bus; wherein the LPC host controller further comprises an address register. The present invention further provides a method for data transmission between LPC devices, comprising the steps of: starting a first cycle through a first LPC bus by an LPC host controller, wherein a first LPC device sends a request to have a transaction with a second LPC device, and inserting a plurality of wait states after the request is received by the LPC host controller; and starting a second cycle through a second LPC bus by the LPC host controller, wherein the LPC host controller has a transaction with the second LPC device according to the request from the first LPC device.

公开(公告)号：US20050154803A1

公开(公告)日：2005-07-14

申请号：US11009881

申请日：2004-12-10

Applicant: Chung-Ching Huang ,  Lin-Hung Chen ,  Hao-Lin Lin

Inventor： Chung-Ching Huang ,  Lin-Hung Chen ,  Hao-Lin Lin

IPC: G06F12/00 ,  G06F13/10 ,  G06F13/28

CPC classification number: G06F13/102

Abstract: A method for accessing a memory of a computer system for BIOS codes optionally performs a detection procedure to realize a maximum memory burst read size of the memory according to a flag value upon the computer system is initialized. For example, the detection procedure is performed when the flag value is logic “1” and the detection procedure is not performed when the flag value is logic “0”. When the detection procedure is performed, read requests with sequentially reduced memory burst read sizes are asserted to the memory one by one until the maximum memory burst read size of the memory is realized. Then, the BIOS codes are read from the memory with the maximum memory burst read size.

Abstract translation: 用于访问用于BIOS代码的计算机系统的存储器的方法可选地执行检测过程，以在计算机系统初始化时根据标志值实现存储器的最大存储器突发读取大小。 例如，当标志值为逻辑“1”时执行检测过程，并且当标志值为逻辑“0”时不执行检测过程。 当执行检测过程时，依次减少的存储器突发读取大小的读取请求被逐个断言给存储器，直到实现存储器的最大存储器突发读取大小。 然后，从具有最大存储突发读取大小的存储器中读取BIOS代码。

公开(公告)号：US20060149886A1

公开(公告)日：2006-07-06

申请号：US11325906

申请日：2006-01-05

Applicant: Lin-Hung Chen ,  Jui-Ming Wei

Inventor： Lin-Hung Chen ,  Jui-Ming Wei

IPC: G06F13/36

CPC classification number: G06F13/385

Abstract: A bus controller and a control method are used in a computer system. In a bus controller, a bus controller main circuit issues a first signal to the central processing unit in response to a bus configuration cycle for announcing a first-level bus that the first group of components is coupled to. A virtual bridge device issues a second signal to the central processing unit in response to the bus configuration cycle for announcing a second-level bus that the second group of components is coupled to. A path selection unit electrically connected to the first and second groups of components via the first-level and second-level buses, respectively, outputs a normal device select signal to one of the first-level and second-level buses while outputting an invalid device select signal to the other of the first-level and second-level buses according to address data of a transaction.

Abstract translation: 在计算机系统中使用总线控制器和控制方法。 在总线控制器中，总线控制器主电路响应于总线配置周期向中央处理单元发出第一信号，用于通知第一组组件耦合到第一组总线。 虚拟桥接设备响应于总线配置周期向中央处理单元发出第二信号，用于通知第二组组件耦合到的二级总线。 经由第一级和第二级总线电连接到第一和第二组分组的路径选择单元将正常的设备选择信号输出到第一级总线和第二级总线之一，同时输出无效设备 根据交易的地址数据将信号选择到另一个第一级和第二级总线。