公开(公告)号：US20250069642A1

公开(公告)日：2025-02-27

申请号：US18941969

申请日：2024-11-08

Applicant: Lodestar Licensing Group LLC

Inventor： Dean D. Gans

IPC: G11C11/406 ,  G11C16/34

Abstract: A method of operating a memory device is provided, comprising determining a number of operations corresponding to a memory location during a first timing period; and scheduling an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold. A memory device is provided, comprising a memory including a memory location; and circuitry configured to: determine a number of operations corresponding to the memory location during a first timing period; and schedule an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold.

公开(公告)号：US12229449B2

公开(公告)日：2025-02-18

申请号：US18466464

申请日：2023-09-13

Applicant: Lodestar Licensing Group LLC

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F3/06 ,  G06F12/02

Abstract: The present disclosure includes apparatuses and methods related to performing background operations in memory. A memory device can be configured to perform background operations while another memory device in a memory system and/or on a common memory module is busy performing commands received from a host coupled to the memory system and/or common memory module. An example apparatus can include a first memory device, wherein the first memory device can include an array of memory cells and a controller configured to perform a background operation on the first memory device in response to detecting a command from a host to a second memory device.

公开(公告)号：US20250056822A1

公开(公告)日：2025-02-13

申请号：US18929236

申请日：2024-10-28

Applicant: Lodestar Licensing Group LLC

Inventor： Toru Tanzawa

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H10B20/00

Abstract: Methods of forming a transistor might include removing portions of a semiconductor to define a semiconductor fin having an upper portion having an uppermost surface at a first level and extending from the first level to a second level, and a lower portion, wider than the upper portion, having an uppermost surface at the second level and extending from the second level to a third level; forming first and second isolation regions at the third level and adjacent the lower portion of the semiconductor fin; forming a first dielectric overlying portions of the semiconductor that are lower than a level between the first level and the second level; forming a second dielectric overlying an exposed portion of the upper portion of the semiconductor fin; forming a conductor overlying the second dielectric; and forming first and second source/drains in the lower portion of the semiconductor fin at the second level.

公开(公告)号：US20250044948A1

公开(公告)日：2025-02-06

申请号：US18920580

申请日：2024-10-18

Applicant: Lodestar Licensing Group, LLC

Inventor： Larry J. Koudele ,  Bruce A. Liikanen ,  Steve Kientz

IPC: G06F3/06 ,  G11C7/04 ,  G11C16/34 ,  G11C29/02

Abstract: A dynamic temperature compensation trim for use in temperature compensating a memory operation on a memory call of a memory component. The dynamic temperature compensation trim is based on a temperature of the memory component and based on in-service data for the memory operation on the memory cell. A register for the memory operation is modified based on the dynamic temperature compensation trim.

公开(公告)号：US12218081B2

公开(公告)日：2025-02-04

申请号：US18356997

申请日：2023-07-21

Applicant: Lodestar Licensing Group, LLC

Inventor： Jivaan Kishore Jhothiraman ,  John M. Meldrim ,  Lifang Xu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Microelectronic devices include a stack structure of insulative structures vertically alternating with conductive structures and arranged in tiers forming opposing staircase structures. A polysilicon fill material substantially fills an opening (e.g., a high-aspect-ratio opening) between the opposing staircase structures. The polysilicon fill material may have non-compressive stress such that the stack structure may be partitioned into blocks without the blocks bending and without contacts—formed in at least one of the polysilicon fill material and the stack structure—deforming, misaligning, or forming electrical shorts with neighboring contacts.

公开(公告)号：US12217813B2

公开(公告)日：2025-02-04

申请号：US17822033

申请日：2022-08-24

Applicant: Lodestar Licensing Group LLC

Inventor： Dong Pan

IPC: G11C29/42 ,  G11C7/06 ,  G11C11/406 ,  G11C29/12 ,  G11C29/20 ,  G11C29/44

Abstract: Counters may be provided for individual word lines of a memory for tracking word line accesses. In some examples, multiple counters may be provided for individual word lines. In some examples, the counters may be included on the word lines. The counters may be incremented responsive to word line accesses in some examples. In some examples, the counters may be incremented responsive for a time period for which a word line is held open. In some examples, the counters may be incremented responsive to both word line accesses and time periods for which the word line is held open. In some examples, count values for the counters may be written back to the counters after incrementing. In some examples, the count values may be written back prior to receiving a precharge command.

公开(公告)号：US12216847B2

公开(公告)日：2025-02-04

申请号：US18376338

申请日：2023-10-03

Applicant: Lodestar Licensing Group LLC

Inventor： Elsie de la Garza Villarreal ,  Claudia A Delaney ,  Madison E. Wale ,  Bhumika Chhabra

IPC: G06F3/038 ,  H04M1/02

Abstract: Methods and apparatuses for a mobile device (e.g., a mobile phone) supporting virtual peripherals are described. The mobile device may include a projecting component configured to project images to external surfaces outside of the mobile device. In some cases, the mobile device may project an image of a document on a first external surface and an image of a keyboard on a second external surface. Moreover, the mobile device may include an imaging component to receive inputs based on sensing an input device overlaid on the projected image (e.g., the keyboard). Accordingly, the mobile device may function as a computer with an external monitor and a keyboard, virtually added to the mobile device. In some cases, the mobile device may serve two or more users or purposes at a time. For example, the mobile device may operate as an infotainment device of a vehicle.

公开(公告)号：US20250037747A1

公开(公告)日：2025-01-30

申请号：US18918668

申请日：2024-10-17

Applicant: Lodestar Licensing Group, LLC

Inventor： Troy A. Manning

IPC: G11C7/22 ,  G06F3/06 ,  G06F7/523 ,  G06F12/00 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4091 ,  H03K19/00 ,  H03K19/1776

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

公开(公告)号：US20250036295A1

公开(公告)日：2025-01-30

申请号：US18918693

申请日：2024-10-17

Applicant: Lodestar Licensing Group, LLC

Inventor： Qing Liang ,  Jun Huang

IPC: G06F3/06 ,  H04L9/32

Abstract: Methods, systems, and devices related to host identification for a memory system are described. A memory system may receive an index value from a host system that is associated with an identification of the host system. The memory system may identify one or more operating parameter associated with the index value based on receiving the index value. The memory system controller may configure the memory system to utilize one or more operating parameters associated with the index value based on identifying the operating parameters. The memory system may output an indication to the host system that the operating parameters associated with the index value are configured to be utilized by the memory system.

公开(公告)号：US12199070B2

公开(公告)日：2025-01-14

申请号：US18351414

申请日：2023-07-12

Applicant: Lodestar Licensing Group, LLC

Inventor： Kunal R. Parekh ,  Paolo Tessariol ,  Akira Goda

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/482 ,  H01L25/00

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.