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公开(公告)号：US07461285B2
公开(公告)日：2008-12-02
申请号：US11395366
申请日：2006-03-31
申请人： Louis J. Nervegna
发明人： Louis J. Nervegna
CPC分类号： G06F1/04
摘要： A free running clock circuit includes a programmable resistor array including a plurality of resistors connected in series. A plurality of transistors are connected to the plurality of resistors wherein each of the plurality of resistors has one of the plurality of transistors associated therewith for connecting a resistor to the first programmable resistor and providing a resistance thereto. A transistor funnel limits leakage currents from a portion of the plurality of transistors to a single transistor of the transistor funnel.
摘要翻译： 一个自由运行的时钟电路包括一个包括串联连接的多个电阻的可编程电阻阵列。 多个晶体管连接到多个电阻器，其中多个电阻器中的每一个具有与其相关联的多个晶体管中的一个，用于将电阻器连接到第一可编程电阻器并提供电阻。 晶体管漏斗限制从多个晶体管的一部分到晶体管漏斗的单个晶体管的泄漏电流。
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公开(公告)号：US20090319814A1
公开(公告)日：2009-12-24
申请号：US12144803
申请日：2008-06-24
CPC分类号： G06F1/3203 , G06F1/12 , G06F1/3225 , G06F1/3275 , G11C5/14 , G11C17/146 , G11C17/18 , Y02D10/14
摘要： A memory power controller comprises a clock generation circuitry for generating a first clock signal and a second clock signal responsive to a source clock and a determination that the source clock has a period greater than a predetermined value. The first clock is generated responsive to a determination that the source clock has a period greater than the predetermined value and the second clock is generated responsive to the determination that the source clock has a period less than the predetermined value. Memory time-out circuitry generates a memory enable/disable signal to control operation of an associated memory responsive to the clock signal and the determination that the source clock has a period greater than the predetermined value. The memory time-out circuitry further synchronizes the memory enable/disable signal with the source clock.
摘要翻译： 存储器功率控制器包括用于响应于源时钟产生第一时钟信号和第二时钟信号的时钟产生电路以及源时钟具有大于预定值的周期的确定。 响应于源时钟具有大于预定值的周期的确定产生第一时钟，并且响应于源时钟具有小于预定值的周期的确定而产生第二时钟。 存储器超时电路产生存储器使能/禁止信号，以响应于时钟信号来控制相关存储器的操作，以及确定源时钟具有大于预定值的周期。 存储器超时电路进一步使存储器使能/禁止信号与源时钟同步。
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公开(公告)号：US07649425B2
公开(公告)日：2010-01-19
申请号：US11395367
申请日：2006-03-31
申请人： Louis J. Nervegna
发明人： Louis J. Nervegna
CPC分类号： H03L1/022 , G06F1/04 , H03J2200/10 , H03K4/501
摘要： A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage. The switching circuit has an inherent temperature profile associated therewith. A voltage divider circuit outputs a defined trip voltage that is compensated over the temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for the free running clock circuit. The voltage divider circuit has a top programmable resistor array connected in series with at least two programmable resistor arrays between two supply terminals of differing voltages.
摘要翻译： 自由运行时钟电路包括用于基于跳闸电压以预定频率在第一和第二逻辑状态之间切换的切换电路。 开关电路具有与其相关联的固有温度分布。 分压器电路输出定义的跳闸电压，其经过温度补偿以偏移所述开关电路的温度分布，以为自由运行时钟电路提供总体温度补偿操作。 分压器电路具有与不同电压的两个电源端子之间的至少两个可编程电阻器阵列串联连接的顶部可编程电阻器阵列。
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公开(公告)号：US08020010B2
公开(公告)日：2011-09-13
申请号：US12144803
申请日：2008-06-24
CPC分类号： G06F1/3203 , G06F1/12 , G06F1/3225 , G06F1/3275 , G11C5/14 , G11C17/146 , G11C17/18 , Y02D10/14
摘要： A memory power controller comprises a clock generation circuitry for generating a first clock signal and a second clock signal responsive to a source clock and a determination that the source clock has a period greater than a predetermined value. The first clock is generated responsive to a determination that the source clock has a period greater than the predetermined value and the second clock is generated responsive to the determination that the source clock has a period less than the predetermined value. Memory time-out circuitry generates a memory enable/disable signal to control operation of an associated memory responsive to the clock signal and the determination that the source clock has a period greater than the predetermined value. The memory time-out circuitry further synchronizes the memory enable/disable signal with the source clock.
摘要翻译： 存储器功率控制器包括用于响应于源时钟产生第一时钟信号和第二时钟信号的时钟产生电路以及源时钟具有大于预定值的周期的确定。 响应于源时钟具有大于预定值的周期的确定产生第一时钟，并且响应于源时钟具有小于预定值的周期的确定而产生第二时钟。 存储器超时电路产生存储器使能/禁止信号，以响应于时钟信号来控制相关存储器的操作，以及确定源时钟具有大于预定值的周期。 存储器超时电路进一步使存储器使能/禁止信号与源时钟同步。
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公开(公告)号：US07385453B2
公开(公告)日：2008-06-10
申请号：US11395378
申请日：2006-03-31
申请人： Louis J. Nervegna
发明人： Louis J. Nervegna
IPC分类号： H03L1/00
CPC分类号： H03K3/0231 , H03K3/011 , H03K3/354
摘要： A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage the switching circuit has a programmable temperature profile associated therewith. The switching circuit includes a comparator circuit that has first and second comparators. The first and second comparators have a reference input connected to receive the trip voltage, and the output of the comparators change logic states between a first logic state and a second logic state when the other input of the comparator passes the trip voltage. The first and second comparators have a programmable offset voltage enabling programming of the programmable voltage supply profile of the switching circuit. An RC timing circuit defines when the outputs of the comparators switch between the first and second logic states by providing a feedback to the other inputs of the two comparators. A temperature compensated trip voltage generator outputs a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit.
摘要翻译： 自由运行时钟电路包括用于基于跳闸电压以预定频率切换第一和第二逻辑状态的切换电路，切换电路具有与其相关联的可编程温度分布。 开关电路包括具有第一和第二比较器的比较器电路。 第一和第二比较器具有连接以接收跳闸电压的参考输入，并且当比较器的另一输入通过跳闸电压时，比较器的输出在第一逻辑状态和第二逻辑状态之间改变逻辑状态。 第一和第二比较器具有可编程失调电压，从而能够编程开关电路的可编程电压供应曲线。 RC定时电路通过向两个比较器的其他输入提供反馈来定义比较器的输出何时在第一和第二逻辑状态之间切换。 温度补偿跳闸电压发生器输出定义的跳闸电压，其经过温度补偿以偏移所述开关电路的温度分布，以为所述自由运行时钟电路提供总体温度补偿操作。
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公开(公告)号：US20070241833A1
公开(公告)日：2007-10-18
申请号：US11395378
申请日：2006-03-31
申请人： Louis J. Nervegna
发明人： Louis J. Nervegna
IPC分类号： H03L1/00
CPC分类号： H03K3/0231 , H03K3/011 , H03K3/354
摘要： A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage the switching circuit has a programmable temperature profile associated therewith. The switching circuit includes a comparator circuit that has first and second comparators. The first and second comparators have a reference input connected to receive the trip voltage, and the output of the comparators change logic states between a first logic state and a second logic state when the other input of the comparator passes the trip voltage. The first and second comparators have a programmable offset voltage enabling programming of the programmable voltage supply profile of the switching circuit. An RC timing circuit defines when the outputs of the comparators switch between the first and second logic states by providing a feedback to the other inputs of the two comparators. A temperature compensated trip voltage generator outputs a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit.
摘要翻译： 自由运行时钟电路包括用于基于跳闸电压以预定频率切换第一和第二逻辑状态的切换电路，切换电路具有与其相关联的可编程温度分布。 开关电路包括具有第一和第二比较器的比较器电路。 第一和第二比较器具有连接以接收跳闸电压的参考输入，并且当比较器的另一输入通过跳闸电压时，比较器的输出在第一逻辑状态和第二逻辑状态之间改变逻辑状态。 第一和第二比较器具有可编程失调电压，从而能够编程开关电路的可编程电压供应曲线。 RC定时电路通过向两个比较器的其他输入提供反馈来定义比较器的输出何时在第一和第二逻辑状态之间切换。 温度补偿跳闸电压发生器输出定义的跳闸电压，其经过温度补偿以偏移所述开关电路的温度分布，以为所述自由运行时钟电路提供总体温度补偿操作。
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公开(公告)号：US20070234097A1
公开(公告)日：2007-10-04
申请号：US11395366
申请日：2006-03-31
申请人： Louis J. Nervegna
发明人： Louis J. Nervegna
IPC分类号： G06F1/00
CPC分类号： G06F1/04
摘要： A free running clock circuit includes a programmable resistor array including a plurality of resistors connected in series. A plurality of transistors are connected to the plurality of resistors wherein each of the plurality of resistors has one of the plurality of transistors associated therewith for connecting a resistor to the first programmable resistor and providing a resistance thereto. A transistor funnel limits leakage currents from a portion of the plurality of transistors to a single transistor of the transistor funnel.
摘要翻译： 一个自由运行的时钟电路包括一个包括串联连接的多个电阻的可编程电阻阵列。 多个晶体管连接到多个电阻器，其中多个电阻器中的每一个具有与其相关联的多个晶体管中的一个，用于将电阻器连接到第一可编程电阻器并提供电阻。 晶体管漏斗限制从多个晶体管的一部分到晶体管漏斗的单个晶体管的泄漏电流。
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