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公开(公告)号:US20060023959A1
公开(公告)日:2006-02-02
申请号:US11158410
申请日:2005-06-21
申请人: Hsing-Chien Yang , Jin-Ming Chen , Lucian-Yuan
发明人: Hsing-Chien Yang , Jin-Ming Chen , Lucian-Yuan
CPC分类号: H04N19/43 , G06F7/544 , G06F2207/5442
摘要: A circuit for computing sums of absolute difference (SAD) is provided. The circuit has an absolute difference circuit, a first adder, a first register and a first selective circuit. The absolute difference circuit receives a first data PMi,j and a second data PSi,j and output a absolute difference data ADi,j, wherein ADi,j=|PMi,j−PSi,j|. The first adder receives and adds the absolute difference data and a first accumulative data, and outputs a first sum. The register receives and locks the first sum according to a first preset timing sequence, and outputs a first sum of absolute difference data. The first selective circuit receives and selects the first sum of absolute difference data or 0, and outputs the selected data as the first accumulative data.
摘要翻译: 提供了一种用于计算绝对差(SAD)和的电路。 电路具有绝对差电路,第一加法器,第一寄存器和第一选择电路。 绝对差分电路接收第一数据PM i i,j and和第二数据PS i,j,并输出绝对差数据AD i i,j / >,其中,AD i,j,i,j,i,j,i,j。 第一加法器接收并添加绝对差数据和第一累积数据,并输出第一和。 寄存器根据第一预设定时序列接收并锁定第一和,并输出绝对差数据的第一和。 第一选择电路接收并选择绝对差数据的第一和或0,并将选择的数据作为第一累积数据输出。
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公开(公告)号:US08416856B2
公开(公告)日:2013-04-09
申请号:US11158410
申请日:2005-06-21
申请人: Hsing-Chien Yang , Jin-Ming Chen , Lucian-Yuan
发明人: Hsing-Chien Yang , Jin-Ming Chen , Lucian-Yuan
CPC分类号: H04N19/43 , G06F7/544 , G06F2207/5442
摘要: A circuit for computing sums of absolute difference (SAD) is provided. The circuit has an absolute difference circuit, a first adder, a first register and a first selective circuit. The absolute difference circuit receives a first data PMi,j and a second data PSi,j and output a absolute difference data ADi,j, wherein ADi,j=|PMi,j−PSi,j|. The first adder receives and adds the absolute difference data and a first accumulative data, and outputs a first sum. The register receives and locks the first sum according to a first preset timing sequence, and outputs a first sum of absolute difference data. The first selective circuit receives and selects the first sum of absolute difference data or 0, and outputs the selected data as the first accumulative data.
摘要翻译: 提供了一种用于计算绝对差(SAD)和的电路。 电路具有绝对差电路,第一加法器,第一寄存器和第一选择电路。 绝对差电路接收第一数据PMi,j和第二数据PSi,j并输出绝对差数据ADi,j,其中ADi,j = | PMi,j-PSi,j |。 第一加法器接收并添加绝对差数据和第一累积数据,并输出第一和。 寄存器根据第一预设定时序列接收并锁定第一和,并输出绝对差数据的第一和。 第一选择电路接收并选择绝对差数据的第一和或0,并将选择的数据作为第一累积数据输出。
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