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公开(公告)号：US08625792B2
公开(公告)日：2014-01-07
申请号：US12353885
申请日：2009-01-14
申请人： An Mei Chen , Jangwon Lee
发明人： An Mei Chen , Jangwon Lee
IPC分类号： H04N7/38
CPC分类号： H04L63/062 , H04L63/0428 , H04L2463/101 , H04N7/1675 , H04N21/23424 , H04N21/26609 , H04N21/4331 , H04N21/4384 , H04N21/44016 , H04N21/4623
摘要： Methods and apparatus to reduce channel switching time. A method for channel switching includes bundling entitlement control messages (ECMs) to generate bundled ECMs that comprise decryption keys associated with a first content channel and one or more additional content channels, respectively, and transmitting the bundled ECMs with the first content channel. An apparatus for channel switching includes key acquisition logic configured to receive bundled ECMs that comprise decryption keys associated with a first content channel and one or more additional content channels, respectively, processing logic configured to receive a request to render a second content channel that is part of the one or more additional content channels, and decryption logic configured to utilize a selected decryption key obtained from the bundled ECMs to decrypt the second content channel.
摘要翻译： 降低通道切换时间的方法和设备。 用于信道切换的方法包括捆绑授权控制消息（ECM）以分别生成包括与第一内容信道和一个或多个附加内容信道相关联的解密密钥的捆绑ECM，以及发送具有第一内容信道的捆绑ECM。 用于信道切换的装置包括密钥获取逻辑，其被配置为分别接收包含与第一内容信道和一个或多个附加内容信道相关联的解密密钥的捆绑ECM，处理逻辑被配置为接收呈现作为部分的第二内容信道的请求 以及被配置为利用从所捆绑的ECM获得的选择的解密密钥来解密所述第二内容信道的解密逻辑。
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3.发明申请公开(公告)号：US20050004962A1
公开(公告)日：2005-01-06
申请号：US10838247
申请日：2004-05-05
申请人： Chi-Cheng Ju
发明人： Chi-Cheng Ju
CPC分类号： G06F17/147
摘要： The present invention provides an input data control method and system for a data processing system. The system comprises at least one basic operation unit (BOU) and is used for transforming one input matrix X into data in a plurality of specified columns in an output matrix Y via an inverse discrete cosine transform procedure. The method generates and outputs a transform control signal together with the input matrix to at least one of the BOUs. A new transform control signal is generated according to the received transform control signal, and outputted together with the input matrix X, to other following BOUs. The step of generating the new transform control signals is repeated until each specific column of the output matrix Y is decoded by a corresponding BOU. A basic operation procedure is then performed, and the received input matrix is decoded to obtain the data in the specified columns corresponding to the transform control signal.
摘要翻译： 本发明提供了一种用于数据处理系统的输入数据控制方法和系统。 该系统包括至少一个基本操作单元（BOU），并且用于经由反离散余弦变换程序将一个输入矩阵X变换为输出矩阵Y中的多个指定列中的数据。 该方法生成并将输入矩阵输出到至少一个BOU的变换控制信号。 根据接收到的变换控制信号生成新的变换控制信号，并与输入矩阵X一起输出到其他后续的BOU。 重复生成新的变换控制信号的步骤，直到输出矩阵Y的每个特定列被相应的BOU解码。 然后执行基本操作过程，并且对接收到的输入矩阵进行解码以获得与变换控制信号相对应的指定列中的数据。
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公开(公告)号：US09286778B2
公开(公告)日：2016-03-15
申请号：US14018624
申请日：2013-09-05
IPC分类号： H04N7/38 , G08B13/196 , G08B29/04
CPC分类号： G08B13/19697 , G08B29/04 , G08B29/046
摘要： A method and system for detecting tampering of a security system component is provided. An analytic alarm indicative of potential tampering with a security system component is received. Data from at least one sensor is received. A computing device is used to analyze the analytic alarm and the data from the at least one sensor to determine whether tampering of the security system component has occurred. A qualified alarm signal is generated when the analysis of the analytic alarm and the data from the at least one sensor is indicative of tampering.
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公开(公告)号：US5844608A
公开(公告)日：1998-12-01
申请号：US764454
申请日：1996-12-12
申请人： Haoping Yu , Greg Alan Kranawetter , Wai-man Lam
发明人： Haoping Yu , Greg Alan Kranawetter , Wai-man Lam
CPC分类号： H04N19/428 , H04N19/423 , H04N19/593 , H04N19/60 , H04N19/61 , H04N19/13 , H04N19/91
摘要： A television receiver includes an MPEG decoder for providing decoded pixel blocks. Decoded pixels are recompressed prior to storage in frame memory. In the recompression process a reference first pixel is compressed as a function of a pixel block parameter. A reconstructed reference pixel value is used in a prediction network when reconstructing remaining pixels of the pixel block prior to display. A first pixel processor accurately compresses a reference pixel which prevents the propagation of a prediction error throughout the reconstructed block.
摘要翻译： 电视接收机包括用于提供解码像素块的MPEG解码器。 解码的像素在存储在帧存储器中之前被再压缩。 在再压缩处理中，参考第一像素被压缩为像素块参数的函数。 当在显示之前重构像素块的剩余像素时，在预测网络中使用重建的参考像素值。 第一像素处理器精确地压缩参考像素，该参考像素防止在整个重建块中传播预测误差。
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公开(公告)号：US08050320B2
公开(公告)日：2011-11-01
申请号：US11704826
申请日：2007-02-09
CPC分类号： H04N19/198 , H04N19/115 , H04N19/126 , H04N19/139 , H04N19/14 , H04N19/149 , H04N19/152 , H04N19/172 , H04N19/196 , H04N19/197 , H04N19/61 , H04N19/63
摘要： A method and apparatus for video rate control for a video encoding system for encoding a video signal includes determining 12 a variance of pixel values over a time t of the video signal and calculating 13 a quantization parameter for the time t using the pixel variance and a number of output bits for the time t and a quantization parameter, pixel variance and a number of output bits used for an immediately previous time t−1.
摘要翻译： 用于对视频信号进行编码的视频编码系统的视频速率控制的方法和装置包括确定12视频信号的时间t上的像素值的方差，并使用像素方差计算13时刻t的量化参数，以及 时间t的输出比特数和量化参数，像素方差和用于紧接前一时刻t-1的输出比特数。
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公开(公告)号：US5103228A
公开(公告)日：1992-04-07
申请号：US713181
申请日：1991-06-10
摘要： 1-Bit signma-delta modulator having a loop filter (5,6,8), a first negative feedback loop (13,7,8) and a second negative feedback loop (14,4,5,6,8). The filter sections 5 and 8 are passive filter elements and filter section 6 is a high-gain active filter element. A circuit of this type makes a very high clock rate possible in the decision switch 10.
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公开(公告)号：US3941924A
公开(公告)日：1976-03-02
申请号：US527128
申请日：1974-11-25
申请人： Teague N. Leiboff
发明人： Teague N. Leiboff
摘要： A single channel transmission and recording system for a scanner having a multi-channel array of dectors having a single delta modulator in the transmission unit and a single delta demodulator in the receiving unit. A plurality of analog signals, such as video signals sensed by infrared detectors, are each fed to an associated channel having an associated switch circuit. A suitable switch logic generator samples the switches in successive ascending order and subsequently in successive descending order. The sampled analog signals of each channel are fed to a signal delta modulator which converts them to a serial train of digital signals. A synchronizing code generator generates a synchronizing code word which is transmitted with the serial train of digital signals to a receiving station where the serial train of digital signals is reconverted to an analog signal similar to the sampled analog signals for display on a suitable device such as a cathode ray tube. A decoder decodes the synchronizing code word to initiate the frames of scan of the cathode ray tube and a suitable counter responsive to the decoder controls the sweep of the frames of scan in accordance with the sampling of each of the channels in successive ascending order and subsequently in successive descending order.
摘要翻译： 一种用于扫描器的单通道传输和记录系统，具有在传输单元中具有单个增量调制器的多通道阵列阵列和接收单元中的单个增量解调器。 多个模拟信号，例如由红外检测器感测到的视频信号，都被馈送到具有相关联的开关电路的相关信道。 合适的开关逻辑发生器按照连续的升序对开关进行采样，并且随后按顺序降序。 每个通道的采样模拟信号被馈送到信号增量调制器，其将它们转换成串行数字信号。 同步码发生器产生与串行数字信号一起发送的同步码字到接收站，其中串行数字信号被重新转换成类似于采样的模拟信号的模拟信号，以在合适的装置上显示，例如 阴极射线管。 解码器解码同步码字以启动阴极射线管的扫描帧，并且响应于解码器的合适的计数器根据每个信道的采样以连续的升序顺序控制扫描帧的扫描，随后 按顺序降序。
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公开(公告)号：US3573364A
公开(公告)日：1971-04-06
申请号：US3573364D
申请日：1969-08-05
申请人： NIPPON ELECTRIC CO
发明人： SHIMAMURA TADAO
CPC分类号： H04N19/00 , H04B14/062
摘要： A band-compressed delta modulated signal communication system for transmitting an information signal admitting of abrupt variations in amplitude is disclosed in accordance with the teachings of the present invention wherein delta modulating means operable at a first frequency and at a first quantizing level generates a first pulse signal representative of gradual variations in the amplitude of said information signal and pulse modulating means responsive to said delta modulating means and operable at a second frequency and at a second quantizing level generates a second pulse signal representative of abrupt variations in the amplitude of said information signal. The first and second pulse signals are transmitted to a receiving station whereat said first and second pulse signals are demodulated to derive first and second analog signals which are combined to reproduce said information signal.
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公开(公告)号：US08416856B2
公开(公告)日：2013-04-09
申请号：US11158410
申请日：2005-06-21
申请人： Hsing-Chien Yang , Jin-Ming Chen , Lucian-Yuan
发明人： Hsing-Chien Yang , Jin-Ming Chen , Lucian-Yuan
CPC分类号： H04N19/43 , G06F7/544 , G06F2207/5442
摘要： A circuit for computing sums of absolute difference (SAD) is provided. The circuit has an absolute difference circuit, a first adder, a first register and a first selective circuit. The absolute difference circuit receives a first data PMi,j and a second data PSi,j and output a absolute difference data ADi,j, wherein ADi,j=|PMi,j−PSi,j|. The first adder receives and adds the absolute difference data and a first accumulative data, and outputs a first sum. The register receives and locks the first sum according to a first preset timing sequence, and outputs a first sum of absolute difference data. The first selective circuit receives and selects the first sum of absolute difference data or 0, and outputs the selected data as the first accumulative data.
摘要翻译： 提供了一种用于计算绝对差（SAD）和的电路。 电路具有绝对差电路，第一加法器，第一寄存器和第一选择电路。 绝对差电路接收第一数据PMi，j和第二数据PSi，j并输出绝对差数据ADi，j，其中ADi，j = | PMi，j-PSi，j |。 第一加法器接收并添加绝对差数据和第一累积数据，并输出第一和。 寄存器根据第一预设定时序列接收并锁定第一和，并输出绝对差数据的第一和。 第一选择电路接收并选择绝对差数据的第一和或0，并将选择的数据作为第一累积数据输出。
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