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    CORRECTING MEMORY DEVICE AND MEMORY CHANNEL FAILURES IN THE PRESENCE OF KNOWN MEMORY DEVICE FAILURES
    1.
    发明申请
    CORRECTING MEMORY DEVICE AND MEMORY CHANNEL FAILURES IN THE PRESENCE OF KNOWN MEMORY DEVICE FAILURES 失效
    在存在的存储器件故障存在的情况下修正存储器件和存储器通道故障

    公开(公告)号：US20120198309A1

    公开(公告)日：2012-08-02

    申请号：US13016977

    申请日：2011-01-29

    申请人： Luiz C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Barry M. Trager

    发明人： Luiz C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Barry M. Trager

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G06F11/10 ,  H03M13/13 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19

    摘要： Correcting memory device (chip) and memory channel failures in the presence of known memory device failures. A memory channel failure is located and corrected, or alternatively up to c chip failures are corrected and up to d chip failures are detected in the presence of up to u chips that are marked as suspect. A first stage of decoding is performed that results in recovering an estimate of correctable errors affecting the data or in declaring an uncorrectable error state. When an uncorrectable error state is declared, a second stage of decoding is performed to attempt to correct u erasures and a channel error in M iterations where the channel location is changed in each iteration. A correctable error is declared in response to exactly one of the M iterations being successful.

    摘要翻译： 在存在已知存储器件故障的情况下更正存储器件（芯片）和存储器通道故障。 存储器通道故障被定位和校正，或者高达c个芯片故障被校正，并且在存在被标记为可疑的最多u个芯片的情况下，检测到高达d个芯片故障。 执行解码的第一阶段，其导致恢复影响数据的可校正错误的估计或者宣告不可校正的错误状态。 当声明不可校正的错误状态时，执行第二级解码以尝试在每次迭代中改变通道位置的M次迭代中纠正擦除和通道错误。 响应正好一个M次迭代成功声明可纠正的错误。

    RAIM system using decoding of virtual ECC
    2.
    发明授权
    RAIM system using decoding of virtual ECC 有权
    RAIM系统使用虚拟ECC的解码

    公开(公告)号：US08549378B2

    公开(公告)日：2013-10-01

    申请号：US12822469

    申请日：2010-06-24

    申请人： Luiz C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Barry M. Trager

    发明人： Luiz C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Barry M. Trager

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1044 ,  G06F11/108 ,  H03M13/19 ,  H03M13/2906 ,  H03M13/3761

    摘要： Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations.

    摘要翻译： 在包括计算机实现的方法的冗余存储器系统中的错误校正和检测，所述方法包括接收包括纠错码（ECC）位的数据，从多个信道接收每个信道包括存储器设备位置处的多个存储器件。 该方法还包括计算数据的综合征; 接收一个频道的频道标识符; 以及从所计算的综合征中去除在所述信道上接收的数据的贡献，所述移除导致频道调整的综合征。 频道调整后的综合征被解码，导致故障存储器件的通道调整的存储器件位置，对应于存储器件位置的通道调整的存储器件位置。

    Correcting memory device and memory channel failures in the presence of known memory device failures
    3.
    发明授权
    Correcting memory device and memory channel failures in the presence of known memory device failures 失效
    在存在已知存储器件故障的情况下更正存储器件和存储器通道故障

    公开(公告)号：US08522122B2

    公开(公告)日：2013-08-27

    申请号：US13016977

    申请日：2011-01-29

    申请人： Luiz C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Barry M. Trager

    发明人： Luiz C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Barry M. Trager

    IPC分类号： H03M13/00

    CPC分类号： G06F11/10 ,  H03M13/13 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19

    摘要： Correcting memory device (chip) and memory channel failures in the presence of known memory device failures. A memory channel failure is located and corrected, or alternatively up to c chip failures are corrected and up to d chip failures are detected in the presence of up to u chips that are marked as suspect. A first stage of decoding is performed that results in recovering an estimate of correctable errors affecting the data or in declaring an uncorrectable error state. When an uncorrectable error state is declared, a second stage of decoding is performed to attempt to correct u erasures and a channel error in M iterations where the channel location is changed in each iteration. A correctable error is declared in response to exactly one of the M iterations being successful.

    摘要翻译： 在存在已知存储器件故障的情况下更正存储器件（芯片）和存储器通道故障。 存储器通道故障被定位和校正，或者高达c个芯片故障被校正，并且在存在被标记为可疑的最多u个芯片的情况下，检测到高达d个芯片故障。 执行解码的第一阶段，其导致恢复影响数据的可校正错误的估计或者宣告不可校正的错误状态。 当声明不可校正的错误状态时，执行第二级解码以尝试在每次迭代中改变通道位置的M次迭代中纠正擦除和通道错误。 响应正好一个M次迭代成功声明可纠正的错误。

    ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM
    4.
    发明申请
    ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM 有权
    冗余存储系统中的错误校正和检测

    公开(公告)号：US20110320918A1

    公开(公告)日：2011-12-29

    申请号：US12822469

    申请日：2010-06-24

    申请人： Luis C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Barry M. Trager

    发明人： Luis C. Alves ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens ,  Barry M. Trager

    IPC分类号： H03M13/07 ,  G06F11/10

    CPC分类号： G06F11/1044 ,  G06F11/108 ,  H03M13/19 ,  H03M13/2906 ,  H03M13/3761

    摘要： Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations.

    摘要翻译： 在包括计算机实现的方法的冗余存储器系统中的错误校正和检测，所述方法包括接收包括纠错码（ECC）位的数据，从多个信道接收每个信道包括存储器设备位置处的多个存储器件。 该方法还包括计算数据的综合征; 接收一个频道的频道标识符; 以及从所计算的综合征中去除在所述信道上接收的数据的贡献，所述移除导致频道调整的综合征。 频道调整后的综合征被解码，导致故障存储器件的通道调整的存储器件位置，对应于存储器件位置的通道调整的存储器件位置。

    System to improve error code decoding using historical information and associated methods
    5.
    发明授权
    System to improve error code decoding using historical information and associated methods 有权
    系统使用历史信息和相关方法改进错误码解码

    公开(公告)号：US08185801B2

    公开(公告)日：2012-05-22

    申请号：US12023445

    申请日：2008-01-31

    申请人： Timothy J. Dell ,  Luis A. Lastras-Montano ,  Barry M. Trager ,  Shmuel Winograd

    发明人： Timothy J. Dell ,  Luis A. Lastras-Montano ,  Barry M. Trager ,  Shmuel Winograd

    IPC分类号： H03M13/00

    CPC分类号： G06F11/1044

    摘要： A system to improve error code decoding using historical information. An example system includes storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system generates a memory rank score for each memory rank. The system also includes an error control decoder that uses the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not.

    摘要翻译： 一种使用历史信息改进错误代码解码的系统。 示例性系统包括分割成存储器排名的存储器，以及用于记录具有每个存储器级别的故障的符号的表。 系统为每个存储器级别生成内存等级分数。 该系统还包括错误控制解码器，当访问每个存储器等级时，使用存储器等级分数，以便确定是否应该纠正错误。

    System to Improve Memory Reliability and Associated Methods
    8.
    发明申请
    System to Improve Memory Reliability and Associated Methods 有权
    提高内存可靠性和相关方法的系统

    公开(公告)号：US20100287445A1

    公开(公告)日：2010-11-11

    申请号：US12023374

    申请日：2008-01-31

    申请人： Timothy J. Dell ,  Luis A. Lastras-Montano ,  Barry M. Trager ,  Shmuel Winograd

    发明人： Timothy J. Dell ,  Luis A. Lastras-Montano ,  Barry M. Trager ,  Shmuel Winograd

    IPC分类号： H03M13/05 ,  G06F11/10 ,  H03M13/07

    CPC分类号： H03M13/1545 ,  G06F11/1044 ,  H03M13/1515

    摘要： A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.

    摘要翻译： 一种用于提高可能包括存储器芯片的计算机系统中的存储器可靠性的系统，并且可以依赖于错误控制编码器来发送用于存储在每个存储器芯片中的码字符号。 来自码字的至少两个符号被分配给每个存储器芯片，因此任何存储器芯片的故障可能影响两个或更多个符号。 该系统还可以包括用于记录每个存储器芯片的码字符号的故障和部分故障的表，因此错误控制编码器可以基于先前的部分故障来校正随后的部分故障。 误差控制编码器能够校正和/或检测更多的误差，如果在表中只有一部分芯片被注意为具有故障，而不是被称为具有故障的全芯片。