公开(公告)号：US6130556A

公开(公告)日：2000-10-10

申请号：US98099

申请日：1998-06-16

申请人： Jonathan Schmitt ,  Gary Hom ,  Luong Hung

发明人： Jonathan Schmitt ,  Gary Hom ,  Luong Hung

IPC分类号： H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/00315

摘要： An integrated circuit buffer includes a core output terminal, a pad terminal, a pad pull-down transistor, a pad pull-up transistor, a pull-down control circuit and a pull-up control circuit. The pad pull-down transistor and the pad pull-up transistor are coupled to the pad terminal and have pull-up and pull-down control terminals, respectively. The pull-down control circuit is coupled between the core output terminal and the pull-down control terminal. The pull-up control circuit is coupled between the core output terminal and the pull-up control terminal. A pull-up voltage protection transistor is coupled in series between the pad pull-up transistor and the pad terminal and has a control terminal which is coupled to the pad terminal through a voltage feedback circuit.

摘要翻译： 集成电路缓冲器包括核心输出端子，焊盘端子，焊盘下拉晶体管，焊盘上拉晶体管，下拉控制电路和上拉控制电路。 焊盘下拉晶体管和焊盘上拉晶体管分别耦合到焊盘端子并具有上拉和下拉控制端子。 下拉控制电路耦合在核心输出端子和下拉控制端子之间。 上拉控制电路耦合在核心输出端子和上拉控制端子之间。 上拉电压保护晶体管串联在焊盘上拉晶体管和焊盘端子之间，并且具有通过电压反馈电路耦合到焊盘端子的控制端子。

公开(公告)号：US5539336A

公开(公告)日：1996-07-23

申请号：US432358

申请日：1995-05-01

申请人： Trung Nguyen ,  George Shing ,  Luong Hung ,  Gary H. Cheung ,  Elias Lozano

发明人： Trung Nguyen ,  George Shing ,  Luong Hung ,  Gary H. Cheung ,  Elias Lozano

IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/0175

CPC分类号： H03K19/00361 ,  H03K17/166

摘要： A driver circuit has a single feedback transistor in the driver transistor well to provide a momentary feedback from source to gate and maintain conductance of the driver transistor during turnoff of the driver transistor and thus reduce ringing oscillation at the transistor source output. An enable/disable signal is applied to control conduction circuitry and the driver transistor and force the output to a high impedance state when the circuit is disabled. Clocked operation of the driver circuit is provided with circuitry merged with a latch. A terminal for receiving a global i.sub.dd test signal controls circuitry removing power to the driver circuit and applying a ground potential to the driver output in response to the global i.sub.dd test signal.

摘要翻译： 驱动器电路在驱动晶体管中具有单反馈晶体管，从而提供从源极到栅极的瞬时反馈，并且在驱动晶体管截止期间保持驱动晶体管的导通，从而减少晶体管源极输出处的振荡振荡。 当禁止电路时，施加使能/禁止信号来控制导通电路和驱动晶体管，并将输出强制为高阻抗状态。 驱动器电路的时钟操作具有与锁存器合并的电路。 用于接收全局idd测试信号的终端控制电路去除驱动电路的电力，并且响应于全局idd测试信号将地电位施加到驱动器输出。

公开(公告)号：US6018257A

公开(公告)日：2000-01-25

申请号：US46781

申请日：1998-03-23

申请人： Luong Hung ,  Gary Hom ,  Corinna Chiu

发明人： Luong Hung ,  Gary Hom ,  Corinna Chiu

IPC分类号： H03K19/003 ,  H03B1/00

CPC分类号： H03K19/00315

摘要： An output drive circuit enables both 5V and 3V devices to be connected to the same bus, without exposing the 3V devices to damage from the 5V signals on the bus. The 3V devices utilize 3V output drives that are tolerant of the 5V signals on the bus. The tolerance is achieved by a circuit design which adjusts internal voltages depending upon the external voltage on the bus. The internal voltage adjustments prevent transistor voltage limits from being exceeded and hence prevent damage from occurring.

摘要翻译： 输出驱动电路使5V和3V器件能够连接到同一总线，而不会使3V器件暴露在总线上的5V信号上。 3V器件采用3V输出驱动器，可容忍总线上的5V信号。 该公差通过电路设计实现，其根据总线上的外部电压调节内部电压。 内部电压调节可以防止超过晶体管电压限制，从而防止发生损坏。