公开(公告)号：US20120195091A1

公开(公告)日：2012-08-02

申请号：US13446584

申请日：2012-04-13

申请人： Jonathan Schmitt

发明人： Jonathan Schmitt

IPC分类号： G11C17/16

CPC分类号： H01L27/105 ,  G11C8/12 ,  G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory device includes an antifuse. The antifuse is configured to program a bit cell of the memory device. The antifuse is configured with a PMOS device

摘要翻译： 存储器件包括反熔丝。 反熔丝被配置为对存储器件的位单元进行编程。 反熔丝由PMOS器件构成

公开(公告)号：US20060097763A1

公开(公告)日：2006-05-11

申请号：US10985289

申请日：2004-11-10

申请人： Jonathan Schmitt ,  Roger Roisen

发明人： Jonathan Schmitt ,  Roger Roisen

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/095

摘要： A delay locked loop generates a voltage on a common node as a function of a phase difference between a reference input and a feedback input. A first voltage-controlled delay line coupled between the reference input and the feedback input and has a first delay, which is controlled by the voltage on the common node. A second voltage-controlled delay line is selectively coupled in series with the first delay line, between the reference input and the feedback input, as a function of a test control input. The second delay line has a second delay, which is controlled by the voltage on the common node.

公开(公告)号：US6028449A

公开(公告)日：2000-02-22

申请号：US906343

申请日：1997-08-05

申请人： Jonathan Schmitt

发明人： Jonathan Schmitt

IPC分类号： G05F3/20 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/00

CPC分类号： G05F3/205 ,  H03K19/00315

摘要： An integrated circuit having a DC current test function operates at a core supply voltage and interfaces at an input-output (I/O) supply voltage. The I/O supply voltage is greater than the core supply voltage. The integrated circuit includes a buffer, a voltage level shifting circuit and a pull-up circuit. The buffer is coupled between a core terminal and a pad terminal. The pad terminal has a voltage swing which is substantially equal to the I/O supply voltage. The voltage level shifting circuit has a test signal input with a voltage swing substantially equal to the core supply voltage and a test signal output with a voltage swing from the I/O supply voltage to a selected bias voltage. The pull-up circuit is coupled to the pad terminal and has a control terminal coupled to the test signal output. The pull-up circuit pulls the pad terminal toward the I/O supply voltage during normal operation and selectively isolates the pad terminal from the I/O supply voltage as a function of the test signal during a DC current test.

摘要翻译： 具有直流电流测试功能的集成电路在核心电源电压下工作，并以输入输出（I / O）电源电压进行接口。 I / O电源电压大于核心电源电压。 集成电路包括缓冲器，电压电平移位电路和上拉电路。 缓冲器耦合在核心终端和焊盘终端之间。 焊盘端子具有基本上等于I / O电源电压的电压摆幅。 电压电平移位电路具有基本上等于核心电源电压的电压摆幅的测试信号输入和从I / O电源电压到所选偏置电压的电压摆幅输出的测试信号。 上拉电路耦合到焊盘端子，并具有耦合到测试信号输出的控制端子。 上拉电路在正常操作期间将焊盘端子拉向I / O电源电压，并在直流电流测试期间根据测试信号选择性地将焊盘端子与I / O电源电压隔离。

公开(公告)号：US09136217B2

公开(公告)日：2015-09-15

申请号：US13608595

申请日：2012-09-10

申请人： Jonathan Schmitt ,  Roy Milton Carlson ,  Yong Lu ,  Owen Hynes

发明人： Jonathan Schmitt ,  Roy Milton Carlson ,  Yong Lu ,  Owen Hynes

IPC分类号： G11C17/00 ,  H01L23/525 ,  H01L27/06 ,  H01L27/10

CPC分类号： H01L23/5252 ,  H01L27/0629 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable memory cell including a thick oxide spacer transistor, a programmable thin oxide anti-fuse disposed adjacent to the thick oxide spacer transistor, and first and second thick oxide access transistors. The thick oxide spacer transistor and first and second thick oxide access transistors can include an oxide layer that is thicker than an oxide layer of the programmable thin oxide anti-fuse. The programmable thin oxide anti-fuse and the thick oxide spacer transistor can be natively doped. The first and second thick oxide access transistors can be doped so as to have standard threshold voltage characteristics.

摘要翻译： 包括厚氧化物间隔晶体管，与厚氧化物隔离晶体管相邻设置的可编程薄氧化物反熔丝以及第一和第二厚氧化物存取晶体管的可编程存储单元。 厚氧化物间隔晶体管和第一和第二厚氧化物存取晶体管可以包括比可编程薄氧化物反熔丝的氧化物层厚的氧化物层。 可编程薄氧化物反熔丝和厚氧化物间隔晶体管可以是本征掺杂的。 可以掺杂第一和第二厚氧化物存取晶体管以具有标准阈值电压特性。

公开(公告)号：US08159895B2

公开(公告)日：2012-04-17

申请号：US13173149

申请日：2011-06-30

申请人： Jonathan Schmitt

发明人： Jonathan Schmitt

IPC分类号： G11C7/00

CPC分类号： H01L27/105 ,  G11C8/12 ,  G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and systems for split threshold voltage programmable bitcells are disclosed and may include selectively programming bitcells in a memory device by applying a high voltage to a gate terminal of the bitcells, where the programming burns a conductive hole in an oxide layer above a higher threshold voltage layer in a memory device. The bitcells may comprise an oxide layer and a doped channel, which may comprise a plurality of different threshold voltage layers. The plurality of different threshold voltage layers may comprise at least one layer with a higher threshold voltage and at least one layer with a lower threshold voltage. The oxide may comprise a gate oxide. The bitcell may comprise an anti-fuse device. The layer with a higher threshold voltage may be separated from an output terminal of the bitcell by the at least one layer with a lower threshold voltage.

摘要翻译： 公开了用于分离阈值电压可编程比特单元的方法和系统，并且可以包括通过向位单元的栅极端施加高电压来选择性地对存储器件中的位单元进行编程，其中编程将氧化层中的导电孔烧在高于高阈值电压 层在内存设备中。 位单元可以包括氧化物层和掺杂沟道，其可以包括多个不同的阈值电压层。 多个不同阈值电压层可以包括具有较高阈值电压的至少一个层和具有较低阈值电压的至少一个层。 氧化物可以包括栅极氧化物。 位单元可以包括反熔丝器件。 具有较高阈值电压的层可以与具有较低阈值电压的至少一个层与位单元的输出端分离。

公开(公告)号：US07796418B2

公开(公告)日：2010-09-14

申请号：US12077600

申请日：2008-03-19

申请人： Jonathan Schmitt ,  Joseph Glenn ,  Douglas Smith ,  Myron Buer

发明人： Jonathan Schmitt ,  Joseph Glenn ,  Douglas Smith ,  Myron Buer

IPC分类号： G11C11/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A disclosed embodiment is a programmable memory cell comprising an elevated ground node having a voltage greater than a common ground node by an amount substantially equal to a voltage drop across a trigger point adjustment element. In one embodiment, the trigger point adjustment element can be a diode. The trigger voltage of the programmable memory cell is raised closer to a supply voltage when current passes through the trigger point adjustment element during a write operation. The programmable memory cell can comprise a pair of cross-coupled inverters, and first and second programmable antifuses that can be coupled to each inverter in the pair of cross-coupled inverters. Since the trigger voltage of the programmable memory cell is raised closer to the supply voltage, a programmed antifuse can easily reach below the trigger voltage and result in a successful write operation even when the supply voltage is a low voltage.

摘要翻译： 所公开的实施例是可编程存储器单元，其包括具有大于公共接地节点的电压的升高的接地节点，其量基本上等于触发点调整元件上的电压降。 在一个实施例中，触发点调节元件可以是二极管。 当写入操作期间电流通过触发点调节元件时，可编程存储器单元的触发电压升高到更接近电源电压。 可编程存储器单元可以包括一对交叉耦合的反相器，以及第一和第二可编程反熔丝，其可耦合到该对交叉耦合的反相器中的每个反相器。 由于可编程存储单元的触发电压升高到更接近电源电压，所编程的反熔丝可以容易地达到低于触发电压，并且即使当电源电压是低电压时也导致成功的写入操作。

公开(公告)号：US20090237974A1

公开(公告)日：2009-09-24

申请号：US12077600

申请日：2008-03-19

申请人： Jonathan Schmitt ,  Joseph Glenn ,  Douglas Smith ,  Myron Buer

发明人： Jonathan Schmitt ,  Joseph Glenn ,  Douglas Smith ,  Myron Buer

IPC分类号： G11C17/00 ,  G11C17/18

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A disclosed embodiment is a programmable memory cell comprising an elevated ground node having a voltage greater than a common ground node by an amount substantially equal to a voltage drop across a trigger point adjustment element. In one embodiment, the trigger point adjustment element can be a diode. The trigger voltage of the programmable memory cell is raised closer to a supply voltage when current passes through the trigger point adjustment element during a write operation. The programmable memory cell can comprise a pair of cross-coupled inverters, and first and second programmable antifuses that can be coupled to each inverter in the pair of cross-coupled inverters. Since the trigger voltage of the programmable memory cell is raised closer to the supply voltage, a programmed antifuse can easily reach below the trigger voltage and result in a successful write operation even when the supply voltage is a low voltage.

摘要翻译： 所公开的实施例是可编程存储器单元，其包括具有大于公共接地节点的电压的升高的接地节点，其量基本上等于触发点调整元件上的电压降。 在一个实施例中，触发点调节元件可以是二极管。 当写入操作期间电流通过触发点调节元件时，可编程存储器单元的触发电压升高到更接近电源电压。 可编程存储器单元可以包括一对交叉耦合的反相器，以及第一和第二可编程反熔丝，其可耦合到该对交叉耦合的反相器中的每个反相器。 由于可编程存储单元的触发电压升高到更接近电源电压，所编程的反熔丝可以容易地达到低于触发电压，并且即使当电源电压是低电压时也导致成功的写入操作。

公开(公告)号：US20090109723A1

公开(公告)日：2009-04-30

申请号：US11933073

申请日：2007-10-31

申请人： Myron BUER ,  Jonathan Schmitt ,  Laurentiu Vasiliu

发明人： Myron BUER ,  Jonathan Schmitt ,  Laurentiu Vasiliu

IPC分类号： G11C17/00

CPC分类号： G11C17/18 ,  G11C11/419 ,  G11C17/146 ,  G11C17/16

摘要： A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side to a second upper fuse and a second lower fuse. When the first upper fuse and second lower fuse are programmed, the storage element outputs a first value. When the second upper fuse and first lower fuse are programmed, the storage element outputs a second value. After programming the upper fuse acts as a pull-up fuse and the lower fuse acts as a pull-down fuse hold the state of the cell.

摘要翻译： 提供了基于四位SRAM的一次性可编程存储单元。 在编程之前，存储单元作为SRAM存储单元工作。 在编程之后，存储器单元作为一次性可编程非易失性存储单元工作。 存储单元包括在第一侧耦合到第一上保险丝和第一下熔丝的存储元件，并且在第二侧耦合到第二上保险丝和第二下保险丝。 当第一上保险丝和第二下保险丝被编程时，存储元件输出第一值。 当第二上保险丝和第一下保险丝被编程时，存储元件输出第二值。 编程后，上保险丝作为上拉保险丝，下保险丝作为下拉保险丝保持电池的状态。

公开(公告)号：US20050057975A1

公开(公告)日：2005-03-17

申请号：US10662188

申请日：2003-09-15

申请人： Jonathan Schmitt ,  Carol Gillies

发明人： Jonathan Schmitt ,  Carol Gillies

IPC分类号： G11C7/22 ,  H03L7/089 ,  H03L7/093 ,  G11C5/00

CPC分类号： G11C29/12015 ,  G11C7/22 ,  G11C7/222 ,  G11C29/028 ,  G11C29/50012 ,  H03L7/0893 ,  H03L7/093

摘要： A phase-locked loop within an integrated circuit assembly is provided. The phase-locked loop includes a plurality of subcells of semiconductor devices arranged in a base layer pattern on base layers of the integrated circuit assembly. One or more metal layers are formed over and interconnect the plurality of semiconductor devices in a metallization pattern. The phase-locked loop has an output frequency range that is changeable with a change to the metallization pattern without a corresponding change to the base layer pattern.

摘要翻译： 提供集成电路组件内的锁相环。 锁相环包括在集成电路组件的基极层上以基层图案布置的多个半导体器件子电池。 在金属化图案中形成多个金属层并在多个半导体器件上互连。 锁相环具有随着对金属化图案的改变而可改变的输出频率范围，而基本层图案没有相应的改变。

公开(公告)号：US06785107B1

公开(公告)日：2004-08-31

申请号：US09888207

申请日：2001-06-22

申请人： Jonathan Schmitt

发明人： Jonathan Schmitt

IPC分类号： H02H320

CPC分类号： H03K19/00315 ,  H03K19/003

摘要： A method of power sequence protection for a level shifter is disclosed that includes the steps of placing the level shifter in a pre-selected state if an input voltage supply is not powered on when an output voltage supply is powered on and releasing the level shifter from the pre-selected state to follow transitions of an input signal when the input voltage supply is powered on.

摘要翻译： 公开了一种用于电平转换器的功率序列保护的方法，其包括以下步骤：如果在输出电压供电通电时将输入电压源未通电，则将电平转换器置于预选状态，并将电平转换器从 当输入电压供电被接通时，预选状态跟随输入信号的转换。