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    Low power static random access memory
    1.
    发明授权
    Low power static random access memory 有权
    低功率静态随机存取存储器

    公开(公告)号：US08659936B2

    公开(公告)日：2014-02-25

    申请号：US12979345

    申请日：2010-12-28

    申请人： Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Wei Hwang ,  Chia-Cheng Chen ,  Wei-Chiang Shih

    发明人： Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Wei Hwang ,  Chia-Cheng Chen ,  Wei-Chiang Shih

    IPC分类号： G11C11/21

    CPC分类号： G11C11/417 ,  G11C11/413

    摘要： A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.

    摘要翻译： 在待机模式和写入模式下，将存储单元阵列保持在低电压状态的SRAM，并在读取模式下将存储单元阵列电源电压提高到高电平。 一种SRAM，包括：至少一个存储单元电路，包括具有至少两个反相器的锁存电路，并且包括用于接收电力的两个电力接收端子; 以及供电电路，用于向存储单元电路提供电力，使得当数据被写入锁存电路时，锁存电路的电力接收端的电压低于预定的电压电平。 在一个实施例中，存储单元电路包括多个数据访问终端，并且数据访问终端分别由至少两个传输晶体管开关器件控制。

    LOW POWER STATIC RANDOM ACCESS MEMORY
    2.
    发明申请
    LOW POWER STATIC RANDOM ACCESS MEMORY 有权
    低功率静态随机存取存储器

    公开(公告)号：US20120008449A1

    公开(公告)日：2012-01-12

    申请号：US12979345

    申请日：2010-12-28

    申请人： Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Wei Hwang ,  Chia-Cheng Chen ,  Wei-Chiang Shih

    发明人： Ching-Te Chuang ,  Hao-I Yang ,  Mao-Chih Hsia ,  Wei Hwang ,  Chia-Cheng Chen ,  Wei-Chiang Shih

    IPC分类号： G11C5/14

    CPC分类号： G11C11/417 ,  G11C11/413

    摘要： A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.

    摘要翻译： 在待机模式和写入模式下，将存储单元阵列保持在低电压状态的SRAM，并在读取模式下将存储单元阵列电源电压提高到高电平。 一种SRAM，包括：至少一个存储单元电路，包括具有至少两个反相器的锁存电路，并且包括用于接收电力的两个电力接收端子; 以及供电电路，用于向存储单元电路提供电力，使得当数据被写入锁存电路时，锁存电路的电力接收端的电压低于预定的电压电平。 在一个实施例中，存储单元电路包括多个数据访问终端，并且数据访问终端分别由至少两个传输晶体管开关器件控制。