公开(公告)号：US5536926A

公开(公告)日：1996-07-16

申请号：US361381

申请日：1994-12-22

Applicant: Masaaki Ikeda ,  Hiroshi Goto ,  Kenji Takemura ,  Hidenobu Umeda ,  Masahiro Yoneda ,  Atsushi Irie ,  Kiyotoshi Ookura ,  Norimasa Yamanaka ,  Hiromi Totani

Inventor： Masaaki Ikeda ,  Hiroshi Goto ,  Kenji Takemura ,  Hidenobu Umeda ,  Masahiro Yoneda ,  Atsushi Irie ,  Kiyotoshi Ookura ,  Norimasa Yamanaka ,  Hiromi Totani

IPC: G02B26/10 ,  G06K7/10

CPC classification number: G06K7/10653 ,  G06K2207/1016

Abstract: An optical scanner and an optical scanning device, an optical sensor unit, a coded data reader, and a POS system employing an optical scanner. The optical comprises an elastically deformable element, a vibrational input segment disposed at a first end of the elastically deformable element, a driven segment disposed at a second end of the elastically deformable element, a vibration source for inducing vibration in the vibrational input segment, whereby the vibration induced in the vibrational input segment produces elastic deformation of the elastically deformable element and consequent movement of the driven segment, and a stop for limiting a range of the movement of the driven segment.

Abstract translation: 光学扫描器和光学扫描装置，光学传感器单元，编码数据读取器和采用光学扫描仪的POS系统。 所述光学元件包括可弹性变形的元件，设置在所述可弹性变形元件的第一端的振动输入段，设置在所述可弹性变形元件的第二端的从动段，用于在所述振动输入段中引起振动的振动源，由此 在振动输入段中引起的振动产生可弹性变形的元件的弹性变形，从而导致从动段的移动，以及用于限制从动段的运动范围的停止。

公开(公告)号：US5292401A

公开(公告)日：1994-03-08

申请号：US44009

申请日：1993-04-08

Applicant: Masahiro Yoneda

Inventor： Masahiro Yoneda

IPC: H01J37/32 ,  H01L21/00

CPC classification number: H01L21/67069 ,  H01J37/3255 ,  H01J37/32568 ,  H01J2237/022 ,  H01J2237/20

Abstract: A fine pattern forming apparatus includes a stage and an opposed electrode at least one of which is made of a magnetic material. A magnetic field is applied to this stage or opposed electrode to provide a predetermined gap between the stage and the opposed electrode for a fine pattern formation. In consequence, optimum etching conditions (including etching uniformity, etch rate and etching direction) can be assured without generating dust. As a result, damage caused by the plasma can be reduced, and the etch rate can be increased.

Abstract translation: 精细图案形成装置包括平台和至少一个由磁性材料制成的相对电极。 向该级或相对电极施加磁场，以在阶段和相对电极之间提供预定的间隙以进行精细图案形成。 因此，可以确保最佳的蚀刻条件（包括蚀刻均匀性，蚀刻速率和蚀刻方向）而不产生灰尘。 结果，可以降低由等离子体引起的损伤，并且可以提高蚀刻速率。

公开(公告)号：US5158861A

公开(公告)日：1992-10-27

申请号：US501568

申请日：1990-03-30

Applicant: Akira Tokui ,  Masahiro Yoneda

Inventor： Akira Tokui ,  Masahiro Yoneda

IPC: G03F7/26 ,  G03F7/38 ,  H01L21/027

CPC classification number: G03F7/38

Abstract: A method of forming a minute pattern with controlled resist profile uses a chemically amplifying type resist and deep UV rays. Microposit SAL601-ER7 is applied on a silicon substrate, to form a resist film of the resist on the silicon substrate. The resist film is selectively irradiated with KrF excimer laser beam by using a photomask. Thereafter, an electric field directed vertically downward is applied to the resist film while the resist film is heated. According to this method, H.sup.+ ions which are a catalyst for cross linking generated in the resist film move vertically downward, so that diffusion of the H.sup.+ ions in the lateral direction during heating can be prevented. Consequently, negative minute patterns having sidewalls formed vertical to the substrate can be provided.

Abstract translation: 用受控抗蚀剂轮廓形成微小图案的方法使用化学放大型抗蚀剂和深紫外线。 将微孔SAL601-ER7施加在硅衬底上，以在硅衬底上形成抗蚀剂的抗蚀剂膜。 通过使用光掩模，用KrF准分子激光束选择性地照射抗蚀剂膜。 此后，在抗蚀剂膜被加热的同时，向抗蚀剂膜施加垂直向下的电场。 根据该方法，作为在抗蚀剂膜中产生的交联催化剂的H +离子垂直向下移动，从而可以防止在加热期间H +离子在横向上的扩散。 因此，可以提供具有垂直于衬底的侧壁的负微小图案。

公开(公告)号：US5079617A

公开(公告)日：1992-01-07

申请号：US405283

申请日：1989-09-11

Applicant: Masahiro Yoneda

Inventor： Masahiro Yoneda

IPC: H01L21/3205 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L23/485 ,  H01L23/52 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/28525 ,  H01L23/485 ,  H01L29/4232 ,  H01L29/456 ,  H01L29/66606 ,  H01L2924/0002

Abstract: A MOS FET comprises a gate electrode and source and drain regions. Conductive layers for electrode are formed on surfaces of the source and drain regions. The conductive layers for electrode are formed by a multilayer structure including a high melting point metal silicide film in contact with the source and drain regions and a polycrystalline silicon layer formed thereon. The gate electrode is formed of polysilicon. The gate electrode has a structure in which part of the gate electrode extends over the conductive layers for electrode formed on the source and drain regions. Such structure reduces the resistance of the interconnection layers for electrodes and realizes reduction in width of the gate electrode. In the manufacturing method, the patterning of the conductive layers for electrodes on the surface of the source/drain regions comprises the steps of etching the polycrystalline silicon layer by dry etching, and etching the high melting point metal silicide layer by wet etching. The wet etching enables etching process without damaging the silicon substrate surface.

Abstract translation: MOS FET包括栅极电极和源极和漏极区域。 用于电极的导电层形成在源区和漏区的表面上。 用于电极的导电层由包括与源极和漏极区域接触的高熔点金属硅化物膜和形成在其上的多晶硅层的多层结构形成。 栅电极由多晶硅形成。 栅极电极具有其中部分栅电极在形成于源区和漏区上的电极导电层延伸的结构。 这种结构降低了用于电极的互连层的电阻，并实现了栅电极的宽度的减小。 在制造方法中，在源极/漏极区域的表面上的电极用导电层的图案化包括通过干蚀刻蚀刻多晶硅层，并通过湿法蚀刻蚀刻高熔点金属硅化物层的步骤。 湿式蚀刻可以蚀刻工艺而不会损坏硅衬底表面。

公开(公告)号：US5258266A

公开(公告)日：1993-11-02

申请号：US925146

申请日：1992-08-06

Applicant: Akira Tokui ,  Masahiro Yoneda

Inventor： Akira Tokui ,  Masahiro Yoneda

IPC: G03F7/38 ,  G03F7/32

CPC classification number: G03F7/38 ,  Y10S430/146

Abstract: A method of forming a minute pattern with controlled resist profile by using chemically amplifying type resist and deep UV ray is disclosed. A positive chemically amplifying type resist is applied on a silicon substrate, to form a resist film of the resist on the silicon substrate. The resist film is selectively irradiated with KrF excimer laser beam by using a photomask. Thereafter, an electric field directed vertically downward is applied to the resist film while the resist film is heated. According to this method, H.sup.+ ions which are catalyst for destroying the dissolution inhibiting capability of the dissolution inhibitor generated in the resist film move vertically downward, so that diffusion of the H.sup.+ ions in the lateral direction during heating can be prevented. Consequently, a positive minute pattern having sidewall formed vertical to the substrate can be provided.

Abstract translation: 公开了通过使用化学放大型抗蚀剂和深紫外线形成具有受控抗蚀剂轮廓的微小图案的方法。 在硅衬底上施加正性化学放大型抗蚀剂，以在硅衬底上形成抗蚀剂的抗蚀剂膜。 通过使用光掩模，用KrF准分子激光束选择性地照射抗蚀剂膜。 此后，在抗蚀剂膜被加热的同时，向抗蚀剂膜施加垂直向下的电场。 根据该方法，用于破坏在抗蚀剂膜中产生的溶解抑制能力的催化剂的H +离子垂直向下移动，从而可以防止在加热期间H +离子在横向上的扩散。 因此，可以提供具有垂直于衬底的侧壁的正微小图案。

公开(公告)号：US5177574A

公开(公告)日：1993-01-05

申请号：US446744

申请日：1989-12-06

Applicant: Masahiro Yoneda

Inventor： Masahiro Yoneda

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10817

Abstract: A capacitor of a semiconductor memory device includes a planar type capacitor portion formed on a surface of an impurity region and a stacked type capacitor portion extending above the gate electrode. The stacked capacitor portion has a three-layer structure of polycrystalline silicon in which upper, lower and side surfaces of a lower electrode are surrounded by a dielectric layer and the upper electrode. A portion of a dielectric layer in the stacked capacitor portion is coupled to another dielectric layer formed on the surface of one impurity region. The capacitor has a planar type capacitor provided in the planar area of occupation of the stacked capacitor portion, whereby the capacitance of the capacitor can be increased without increasing the planar area of occupation.

Abstract translation: 半导体存储器件的电容器包括形成在杂质区域的表面上的平面型电容器部分和在栅电极上方延伸的层叠型电容器部分。 叠层电容器部分具有多层硅的三层结构，其中下电极的上，下和侧表面被电介质层和上电极包围。 层叠电容器部分中的介电层的一部分耦合到形成在一个杂质区域的表面上的另一电介质层。 电容器具有设置在层叠电容器部分的占用的平面区域中的平面型电容器，由此可以增加电容器的电容，而不增加占用的平面面积。

公开(公告)号：US5175118A

公开(公告)日：1992-12-29

申请号：US787862

申请日：1991-11-05

Applicant: Masahiro Yoneda

Inventor： Masahiro Yoneda

IPC: H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L23/485 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L21/76897 ,  H01L21/28525 ,  H01L23/485 ,  H01L29/4232 ,  H01L29/456 ,  H01L29/66606 ,  H01L2924/0002

Abstract: A MOS FET comprises a gate electrode and source and drain regions. Conductive layers for electrode are formed on surfaces of the source and drain regions. The conductive layers for electrode are formed by a multilayer structure including a high melting point metal silicide film in contact with the source and drain regions and a polycrystaline silicon layer formed thereon. The gate electrode is formed of polysilicon. The gate electrode has a structure in which part of the gate electrode extends over the conductive layers for electrode formed on the source and drain regions. Such structure reduces the resistance of the interconnection layers for electrodes and realizes reduction in width of the gate electrode. In the manufacturing method, the patterning of the conductive layers for electrodes on the surface of the source/drain regions comprises the steps of etching the polycrystalline silicon layer by dry etching, and ethcing the high melting point metal silicide layer by wet etching. The wet etching enables etching process without damaging the silicon substrate surface.

Abstract translation: MOS FET包括栅极电极和源极和漏极区域。 用于电极的导电层形成在源区和漏区的表面上。 用于电极的导电层由包括与源区和漏区接触的高熔点金属硅化物膜和形成在其上的多晶硅层的多层结构形成。 栅电极由多晶硅形成。 栅极电极具有其中部分栅电极在形成于源区和漏区上的电极导电层延伸的结构。 这种结构降低了用于电极的互连层的电阻，并实现了栅电极的宽度的减小。 在制造方法中，用于在源/漏区表面上的电极用导电层的图案化包括通过干蚀刻蚀刻多晶硅层，并通过湿法蚀刻来对高熔点金属硅化物层进行掺杂的步骤。 湿式蚀刻可以蚀刻工艺而不会损坏硅衬底表面。

公开(公告)号：US4887137A

公开(公告)日：1989-12-12

申请号：US170028

申请日：1988-03-04

Applicant: Masahiro Yoneda ,  Masahiro Hatanaka ,  Yoshio Kohno ,  Shinichi Satoh ,  Hidekazu Oda ,  Koichi Moriizumi

Inventor： Masahiro Yoneda ,  Masahiro Hatanaka ,  Yoshio Kohno ,  Shinichi Satoh ,  Hidekazu Oda ,  Koichi Moriizumi

IPC: H01L23/528 ,  H01L27/108

CPC classification number: H01L27/10829 ,  H01L23/528 ,  H01L27/10805 ,  H01L2924/0002 ,  Y10S257/911

Abstract: A semiconductor memory device comprises four memory cells (4a, 6) arranged in point symmetry on a semiconductor substrate (1), and an insulating layer (10) covering the memory cells and having one contact hole (2) placed in the center of the point symmetry, with the contact hole enabling electrical connection to each of the memory cells.

Abstract translation: 半导体存储器件包括在半导体衬底（1）上以点对称布置的四个存储单元（4a，6）和覆盖存储单元的绝缘层（10），并且具有一个接触孔（2） 点对称，其中接触孔能够电连接到每个存储单元。

公开(公告)号：US5366834A

公开(公告)日：1994-11-22

申请号：US56934

申请日：1993-05-05

Applicant: Masahiro Yoneda ,  Shoichi Bando ,  Ichiro Takeoka

Inventor： Masahiro Yoneda ,  Shoichi Bando ,  Ichiro Takeoka

IPC: C09K11/02 ,  G03C5/00

CPC classification number: C09K11/025

Abstract: In a cathode-ray tube phosphor, a layer consisting of a substantially uniform SiO.sub.2 film or an organic film consisting essentially of at least one type of a polymer selected from the group consisting of an acrylic resin, gelatin, alginic acid, chitosan, and a urea resin is formed as a first layer on the surface of a phosphor particle, and a layer containing at least one type of a metal selected from the group consisting of Zn, Al, and an alkali earth metal and at least one member selected from the group consisting of a colloidal silica, an alumina sol, and a titania sol each having a particle size of 50 nm or less is formed as a second layer on the first layer. This phosphor is excellent in oxidation resistance and dispersibility.

Abstract translation: 在阴极射线管荧光体中，由基本上均匀的SiO 2膜或基本上由至少一种选自丙烯酸树脂，明胶，藻酸，壳聚糖和 尿素树脂在荧光体颗粒的表面上形成为第一层，并且含有选自Zn，Al和碱土金属的至少一种类型的金属和选自以下的至少一种： 在第一层上形成作为第二层的由粒径为50nm以下的胶体二氧化硅，氧化铝溶胶和二氧化钛溶胶构成的组。 该荧光体的耐氧化性和分散性优异。

公开(公告)号：US5228940A

公开(公告)日：1993-07-20

申请号：US865648

申请日：1992-04-10

Applicant: Masahiro Yoneda

Inventor： Masahiro Yoneda

IPC: H01J37/32 ,  H01L21/00

CPC classification number: H01L21/67069 ,  H01J37/3255 ,  H01J37/32568 ,  H01J2237/022 ,  H01J2237/20

Abstract: A fine pattern forming apparatus includes a stage and an opposed electrode at least one of which is made of a magnetic material. A magnetic field is applied to this stage or opposed electrode to provide a predetermined gap between the stage and the opposed electrode for a fine pattern formation. In consequence, optimum etching conditions (including etching uniformity, etch rate and etching direction) can be assured without generating dust. As a result, damage caused by the plasma can be reduced, and the etch rate can be increased.

Abstract translation: 精细图案形成装置包括平台和至少一个由磁性材料制成的相对电极。 向该级或相对电极施加磁场，以在阶段和相对电极之间提供预定的间隙以进行精细图案形成。 因此，可以确保最佳的蚀刻条件（包括蚀刻均匀性，蚀刻速率和蚀刻方向）而不产生灰尘。 结果，可以降低由等离子体引起的损伤，并且可以提高蚀刻速率。