公开(公告)号：US08504862B2

公开(公告)日：2013-08-06

申请号：US12184075

申请日：2008-07-31

申请人： Masato Tomita

发明人： Masato Tomita

IPC分类号： G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00

CPC分类号： H04L7/04 ,  G06F1/12 ,  H03L7/095 ,  H03L7/107 ,  H03L7/1075 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0083 ,  H04L7/033

摘要： A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.

摘要翻译： 一种用于防止CDR电路中的缺陷妨碍连接节点之间的同步并防止连接故障的方法和装置。 CDR电路从接收的数据生成同步时钟。 当从接收到接收到的数据的接收开始的第一预定时间过去时，连接失败处理器执行连接失败处理，如果在连接节点之间的同步时钟不建立，则连接失败处理器执行连接失败处理。 如果当从接收到的数据的接收开始的时间比第一预定时间短的第二预定时间过去时，校正处理器校正了基于连接节点之间的同步时钟的同步的CDR电路的操作。

公开(公告)号：US20090129303A1

公开(公告)日：2009-05-21

申请号：US12199298

申请日：2008-08-27

申请人： Masato TOMITA ,  Takashi SHIMIZU ,  Hideaki WATANABE

发明人： Masato TOMITA ,  Takashi SHIMIZU ,  Hideaki WATANABE

IPC分类号： G08C17/00

CPC分类号： H04L25/0264 ,  H03K5/08 ,  H04L25/0272 ,  H04L25/028

摘要： A data transmission circuit transmitting an activation signal prior to a data signal through a signal transmission line, including: an activation detection signal generation unit for generating an activation detection signal by detecting the activation signal; and a wakeup signal generation unit for being activated by the activation detection signal, and generating a wakeup signal by detecting that the activation signal is transmitted for a predetermined time.

摘要翻译： 数据传输电路通过信号传输线在数据信号之前传输激活信号，包括：激活检测信号产生单元，用于通过检测激活信号产生激活检测信号; 以及唤醒信号生成单元，用于由激活检测信号激活，并且通过检测到激活信号在预定时间内发送来产生唤醒信号。

公开(公告)号：US20080310570A1

公开(公告)日：2008-12-18

申请号：US12184075

申请日：2008-07-31

申请人： Masato TOMITA

发明人： Masato TOMITA

IPC分类号： H04L7/00

CPC分类号： H04L7/04 ,  G06F1/12 ,  H03L7/095 ,  H03L7/107 ,  H03L7/1075 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0083 ,  H04L7/033

摘要： A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.

摘要翻译： 一种用于防止CDR电路中的缺陷妨碍连接节点之间的同步并防止连接故障的方法和装置。 CDR电路从接收的数据生成同步时钟。 当从接收到接收到的数据的接收开始的第一预定时间过去时，连接失败处理器执行连接失败处理，如果在连接节点之间的同步时钟不建立，则连接失败处理器执行连接失败处理。 如果当从接收到的数据的接收开始的时间比第一预定时间短的第二预定时间过去时，校正处理器校正了基于连接节点之间的同步时钟的同步的CDR电路的操作。

公开(公告)号：US20080201598A1

公开(公告)日：2008-08-21

申请号：US12034410

申请日：2008-02-20

申请人： Masato TOMITA

发明人： Masato TOMITA

IPC分类号： G06F1/12

CPC分类号： G06F1/12 ,  H04L7/0004 ,  H04L7/0083 ,  H04L7/033 ,  H04L7/04

摘要： A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.

摘要翻译： 一种用于防止CDR电路中的缺陷妨碍连接节点之间的同步并防止连接故障的方法和装置。 CDR电路从接收的数据生成同步时钟。 当从接收到接收到的数据的接收开始的第一预定时间过去时，连接失败处理器执行连接失败处理，如果在连接节点之间的同步时钟不建立，则连接失败处理器执行连接失败处理。 如果当从接收到的数据的接收开始的时间比第一预定时间短的第二预定时间过去时，校正处理器校正了基于连接节点之间的同步时钟的同步的CDR电路的操作。

公开(公告)号：US06477605B1

公开(公告)日：2002-11-05

申请号：US09262007

申请日：1999-03-04

申请人： Nobuhiro Taki ,  Hideo Makabe ,  Masato Tomita

发明人： Nobuhiro Taki ,  Hideo Makabe ,  Masato Tomita

IPC分类号： G06F1300

CPC分类号： G06F1/3209 ,  G06F1/325 ,  Y02D50/20

摘要： A connection device for connecting electronic devices via a network allows activates its status signal in response to a data transfer operation or in response to receiving a remote status signal. By limiting the activation of the status signal, the connection device reduces the power consumption of the electronic devices. The connection device also performs plug-and-play initialization to prevent device conflicts and allow for hot plug-in of electronic devices.

摘要翻译： 用于经由网络连接电子设备的连接装置允许响应于数据传送操作或响应于接收到远程状态信号来激活其状态信号。 通过限制状态信号的激活，连接装置降低了电子设备的功耗。 连接设备还执行即插即用初始化，以防止设备冲突，并允许热插拔电子设备。

公开(公告)号：US5877907A

公开(公告)日：1999-03-02

申请号：US723669

申请日：1996-09-30

申请人： Hideaki Tanishima ,  Noriko Tomita ,  Masato Tomita

发明人： Hideaki Tanishima ,  Noriko Tomita ,  Masato Tomita

IPC分类号： G11B20/10 ,  G11B20/12 ,  G11B20/06 ,  G11B5/09

CPC分类号： G11B20/10 ,  G11B20/1258

摘要： An apparatus for demodulating a data signal read from a recording medium, in which data is recorded on at least a portion of the recording medium. The data is recorded using a recording system having a substantially constant linear velocity. In this manner, the recording medium is rotated at a substantially constant speed during the reading of data signals such that one of a frequency and an amplitude of the read data signal varies. The apparatus includes a signal processor for processing the read data signal in response to a change in one of the frequency and amplitude to produce a processed data signal suitable for demodulation. Once the processed data signal is produced, a demodulator operates to demodulate the data signal and to produce a demodulated data signal.

摘要翻译： 一种用于解调从记录介质读取的数据信号的装置，其中数据被记录在记录介质的至少一部分上。 使用具有基本恒定的线速度的记录系统记录数据。 以这种方式，在数据信号的读取期间，记录介质以基本恒定的速度旋转，使得读取的数据信号的频率和幅度之一变化。 该装置包括信号处理器，用于响应于频率和幅度之一的变化来处理读取的数据信号，以产生适合于解调的经处理的数据信号。 一旦产生经处理的数据信号，解调器就操作以解调数据信号并产生解调数据信号。

公开(公告)号：US20130287154A1

公开(公告)日：2013-10-31

申请号：US13927831

申请日：2013-06-26

申请人： Masato TOMITA

发明人： Masato TOMITA

IPC分类号： H04L7/04

CPC分类号： H04L7/04 ,  G06F1/12 ,  H03L7/095 ,  H03L7/107 ,  H03L7/1075 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0083 ,  H04L7/033

摘要： A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.

摘要翻译： 一种用于防止CDR电路中的缺陷妨碍连接节点之间的同步并防止连接故障的方法和装置。 CDR电路从接收的数据生成同步时钟。 当从接收到接收到的数据的接收开始的第一预定时间过去时，连接失败处理器执行连接失败处理，如果在连接节点之间的同步时钟不建立，则连接失败处理器执行连接失败处理。 如果当从接收到的数据的接收开始的时间比第一预定时间短的第二预定时间过去时，校正处理器校正了基于连接节点之间的同步时钟的同步的CDR电路的操作。

公开(公告)号：USD563813S1

公开(公告)日：2008-03-11

申请号：US29274424

申请日：2007-04-24

申请人： Masato Tomita ,  Tatsutoshi Kobayakawa

设计人： Masato Tomita ,  Tatsutoshi Kobayakawa

公开(公告)号：US06790208B2

公开(公告)日：2004-09-14

申请号：US09812461

申请日：2001-03-20

申请人： Kazuya Oribe ,  Masato Tomita ,  Hiroshi Takamido ,  Noriyuki Ina

发明人： Kazuya Oribe ,  Masato Tomita ,  Hiroshi Takamido ,  Noriyuki Ina

IPC分类号： A61F504

CPC分类号： A61B17/7083

摘要： A slider 37 having a rod-pressing portion 35 for pressing a rod 23 into a rod-engaging recess 25 is movably provided on a holder body 27 having the rod-engaging recess 25. The holder body 27 includes a pressing state holding mechanism for relatively moving the slider 37 with respect to the holder body 27 to hold the rod 23 in a state in which the rod 23 is pressed against the rod-engaging recess 25 by the rod-pressing portion 35. The pressing state holding mechanism includes a screw rod movably, detachably and threadedly engaged with a screw hole formed in the holder body 27. A tip end of the screw rod 45 and the slider 37 connected to each other such that they permit rotation of the screw rod 45 with respect to the slider 37 but move integrally with respect to the holder body 27, and the slider 37 can be attached to and detached from the slider 37.

摘要翻译： 具有用于将杆23按压到杆接合凹部25中的杆按压部35的滑块37可移动地设置在具有杆接合凹部25的保持器主体27上。保持器主体27包括用于相对的按压状态保持机构 相对于保持器主体27移动滑块37，以将杆23保持在杆23通过杆按压部分35压靠在杆接合凹部25上的状态。按压状态保持机构包括螺杆 可移动地，可拆卸地并且与形成在保持器主体27中的螺纹孔螺纹接合。螺杆45的前端和滑块37彼此连接，使得它们允许螺杆45相对于滑块37旋转，但是 相对于保持器主体27一体地移动，并且滑块37可以附接到滑块37并从滑动件37拆下。

公开(公告)号：US08543171B2

公开(公告)日：2013-09-24

申请号：US12199298

申请日：2008-08-27

申请人： Masato Tomita ,  Takashi Shimizu ,  Hideaki Watanabe

发明人： Masato Tomita ,  Takashi Shimizu ,  Hideaki Watanabe

IPC分类号： H04M1/00

CPC分类号： H04L25/0264 ,  H03K5/08 ,  H04L25/0272 ,  H04L25/028

摘要： A data transmission circuit transmitting an activation signal prior to a data signal through a signal transmission line, including: an activation detection signal generation unit for generating an activation detection signal by detecting the activation signal; and a wakeup signal generation unit for being activated by the activation detection signal, and generating a wakeup signal by detecting that the activation signal is transmitted for a predetermined time.

摘要翻译： 数据传输电路通过信号传输线在数据信号之前传输激活信号，包括：激活检测信号产生单元，用于通过检测激活信号产生激活检测信号; 以及唤醒信号生成单元，用于由激活检测信号激活，并且通过检测到激活信号在预定时间内发送来产生唤醒信号。