公开(公告)号：US5917729A

公开(公告)日：1999-06-29

申请号：US964318

申请日：1997-11-04

申请人： Masayuki Naganuma ,  Tetsu Tanizawa

发明人： Masayuki Naganuma ,  Tetsu Tanizawa

IPC分类号： H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118

CPC分类号： G06F17/5068

摘要： A method of placing and routing elements of a semiconductor integrated circuit picks out a signal net, a driver of the signal net, and load cells driven by the driver among the elements of the integrated circuit, places the driver at a first position, defines a first range based on the first position, determines a second position in the first range, defines a second range based on the second position, and collectively places the load cells of a predetermined number in the second range. Namely, the method deals with a signal net in the integrated circuit, a driver of the net, and load cells driven by the driver. The method sets conditions on the signal net, driver, and load cells, when placing and routing the elements of the integrated circuit, to thereby reduce skew (skew time), wiring overhead, and time delay in the integrated circuit and speedily and easily place and route the elements.

摘要翻译： 放置和布线半导体集成电路的元件的方法从集成电路的元件中选出信号网，信号网的驱动器和由驱动器驱动的负载单元，将驱动器置于第一位置，定义一个 基于第一位置的第一范围确定第一范围中的第二位置，基于第二位置限定第二范围，并且将预定数量的称重传感器集中地放置在第二范围内。 即，该方法处理集成电路中的信号网，网络的驱动器和由驱动器驱动的负载传感器。 该方法在放置和布线集成电路的元件时，对信号网，驱动器和称重传感器设置条件，从而减少集成电路中的偏斜（歪斜时间），接线开销和时间延迟，并快速方便地放置 并路由元素。

公开(公告)号：US5221342A

公开(公告)日：1993-06-22

申请号：US766892

申请日：1991-09-25

申请人： Takashi Minami ,  Masayuki Naganuma ,  Yoshiaki Yagita ,  Takeshi Kawaura ,  Eiko Kinoshita

发明人： Takashi Minami ,  Masayuki Naganuma ,  Yoshiaki Yagita ,  Takeshi Kawaura ,  Eiko Kinoshita

IPC分类号： A61K8/23 ,  A61Q1/02 ,  A61Q1/06 ,  A61Q1/08 ,  A61Q1/10 ,  A61Q1/12 ,  A61Q3/02

CPC分类号： A61Q3/02 ,  A61K8/23 ,  A61Q1/02 ,  A61Q1/06 ,  A61Q1/08 ,  A61Q1/10 ,  A61Q1/12 ,  A61K2800/43

摘要： A coloring composition comprising (i) gypsum dihydrate and (ii) at least one coloring agent selected from the group consisting of inorganic pigments, organic pigments, dyestuffs, and natural coloring matters. This coloring composition may be produced by mixing (i) gypsum having, as water of crystallization, 0 to 0.5 mole, based on one mole of the gypsum, of water, (ii) at least one coloring agent selected from the group consisting inorganic pigments, organic pigments, dyestuffs, and natural coloring matters, and (iii) water or an aqueous solvent solution, and after solidification, powdering the resultant solid mixture.The coloring composition can provide a clear color tone when formulated in, for example, cosmetics, and when completely dispersed in, for example, a cosmetic base material.

摘要翻译： 一种着色组合物，其包含（i）二水合石膏和（ii）至少一种选自无机颜料，有机颜料，染料和天然着色剂的着色剂。 该着色组合物可以通过将（i）结晶水作为1摩尔石膏为0至0.5摩尔的水，（ii）至少一种选自无机颜料的着色剂 有机颜料，染料和天然着色剂，和（iii）水或溶剂水溶液，固化后粉碎所得固体混合物。 当配制在例如化妆品中时，并且当完全分散在例如化妆品基材中时，着色组合物可以提供清晰的色调。

公开(公告)号：US4827159A

公开(公告)日：1989-05-02

申请号：US58313

申请日：1987-06-05

申请人： Masayuki Naganuma

发明人： Masayuki Naganuma

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/0952 ,  H03K19/17 ,  H03K17/16

CPC分类号： H03K19/00361 ,  H03K19/0013

摘要： A CMOS output buffer circuit is reduced its output pulse noise and excess current which runs through the CMOS when it is switched ON and OFF. In the gate circuits of p and n channel FETs of the CMOS output buffer circuit, a time constant circuit is inserted. The time constant circuit slightly slows down the voltage variation of input signals to the gates, so the rush current which runs through the output FETs for charging up or discharging the load capacitance is decreased. So, the dI/dt noise is reduced, but the total switching time of the output circuit is not so much affected. By the difference of time lags between the build up and trailing edges of input pulses for both output FETs, one of the output FETs becomes conductive always after the other one is cut off. So, the excess current is reduced. The time constant circuit is composed of a series connected resistor and inverter circuit, connected between positive and negative voltage sources. The time constant circuit many be provided in both or one of the driving circuits for the output FETs. The resistors may be replaced by FETs having proper internal resistances.

摘要翻译： CMOS输出缓冲电路在其接通和断开时可以减小其输出脉冲噪声和超过CMOS的过电流。 在CMOS输出缓冲电路的p沟道FET和n沟道FET的栅极电路中插入时间常数电路。 时间常数电路将输入信号的电压变化略微减慢到门，因此通过输出FET的冲击电流用于对负载电容充电或放电。 因此，dI / dt噪声降低，但输出电路的总开关时间不会受到太大的影响。 由于两个输出FET的输入脉冲的上升沿和下降沿之间的时间差的差异，一个输出FET在另一个输出FET被切断之后总是导通。 因此，过剩电流减少。 时间常数电路由串联的电阻和反相电路组成，连接在正，负电压源之间。 时间常数电路很多被提供在用于输出FET的驱动电路的两个或一个中。 电阻可以由具有适当内部电阻的FET代替。

公开(公告)号：US4825107A

公开(公告)日：1989-04-25

申请号：US155574

申请日：1988-02-12

申请人： Masayuki Naganuma ,  Yoshiyuki Suehiro

发明人： Masayuki Naganuma ,  Yoshiyuki Suehiro

IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L23/525 ,  H01L27/04 ,  H01L27/118 ,  H03K3/01 ,  H01L27/00 ,  H03K17/04 ,  H03K19/01

CPC分类号： H01L27/11898 ,  H01L23/525 ,  H01L2924/0002

摘要： A master slice type integrated circuit for providing various circuits by altering the routing of interconnections comprises a plurality of input/output cells arranged in a peripheral region on a semiconductor chip, the input/output cells each comprising pads for connection with an external circuit, input wiring regions each for accommodating input interconnecting lines transmitting input signals applied to the pads, and output circuit regions each for forming output buffers; and a plurality of basic cells being arranged in a region on the chip surrounded by the arrangement of the input/output cells. Two adjacent input/output cells are paired with each other. The output circuit regions of the pair of the input/output cells are arranged in the vicinity of a boundary of the pair. The input wiring regions of the pair are arranged in the vicinity of boundaries with respect to other pairs.