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1.发明授权ROM burst transfer continuous read-out extension method and a microcomputer system with a built-in ROM using this method 失效ROM突发传输连续读出扩展方法和使用此方法的内置ROM的微机系统
公开(公告)号：US5550996A
公开(公告)日：1996-08-27
申请号：US143779
申请日：1993-11-01
申请人： Masue Shiba , Shigeharu Nakata
发明人： Masue Shiba , Shigeharu Nakata
CPC分类号： G06F12/0215 , G06F12/0607
摘要： A microcomputer with a built-in ROM for a burst transfer method has a ROM divided into blocks, for reading data by being supplied with an address, a first control circuit for supplying the address to the ROM, an adder for adding a specific address value to the address and outputting an added address which is the result of the addition, a comparator for comparing the next supplied address and the added address and outputting the result of the comparison, a second control circuit for supplying a control signal indicating to the first control circuit that a burst transfer will or will not be executed, based on the result of the comparison output by the comparator, and a selector for selecting data output from each block and outputting the data to a bus. In the microcomputer, the address includes selection data for selecting any of the blocks, and the address and the added address are input to the blocks, so that data corresponding to the address or the added address is input in accordance with the selection data in the address. The selector selects and outputs the output data from the blocks in accordance with the selection data in the address. The first control circuit controls the timing of the supply of the address so that it is synchronized with the read-out timing of the ROM based on the control signal supplied from the second control circuit.
摘要翻译： 具有用于突发传送方法的内置ROM的微计算机具有ROM，被划分为块，用于通过提供地址来读取数据，用于向ROM提供地址的第一控制电路，用于将特定地址值 输出地址并输出作为相加结果的附加地址;比较器，用于比较下一提供的地址和相加地址，并输出比较结果;第二控制电路，用于提供指示第一控制的控制信号 基于比较器输出的比较结果，以及用于选择从每个块输出的数据并将数据输出到总线的选择器，突发传送将被执行或将不被执行的电路。 在微型计算机中，地址包括用于选择任何块的选择数据，并且将地址和相加的地址输入到块，使得与地址或添加的地址相对应的数据根据 地址。 选择器根据地址中的选择数据从块中选择并输出输出数据。 第一控制电路基于从第二控制电路提供的控制信号控制提供地址的定时，使其与ROM的读出定时同步。
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公开(公告)号：US08407801B2
公开(公告)日：2013-03-26
申请号：US13167821
申请日：2011-06-24
IPC分类号： H04L29/06
CPC分类号： G06F21/577 , H04L63/1441 , H04L63/20
摘要： In a security countermeasure function evaluation apparatus, an estimator operates an input unit, whereby an evaluation point calculation unit makes an evaluation as to whether each item of countermeasure information representing a security countermeasure function in detail satisfies each item of sufficient condition table information, and the evaluation point is calculated from the evaluation result of each item, whereby the transition probability calculation unit calculates a transition probability based on the evaluation point.
摘要翻译： 在安全对策功能评价装置中，估计器操作输入单元，由此评估点计算单元对表示安全对策功能的每个对策信息的每个项目是否详细满足每个充足条件表信息的项目进行评估，并且 根据各项目的评价结果计算评价点，由此，转移概率计算部基于评价点来计算转移概率。
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公开(公告)号：US5511222A
公开(公告)日：1996-04-23
申请号：US375009
申请日：1995-01-18
申请人： Masue Shiba , Shigeharu Nakata
发明人： Masue Shiba , Shigeharu Nakata
CPC分类号： G06F7/74
摘要： A priority encoder-includes an encoder for coding an input consisting of a plurality of bits, selectors, respectively provided for bit input terminals of the encoder, for respectively receiving corresponding ones of a plurality of bits of an operand input, each of the selectors including a switch circuit to be controlled by an operand input bit, a carry line connected in series with the switch circuit and connected in series with all of the selectors, a first precharge circuit, connected to a carry line portion on one end side of the switch circuit, for precharging the carry line at a predetermined timing, a first detector which is controlled by an enable signal for designating upper bit priority and detects whether a potential of a carry line portion on an upper bit side of the switch circuit is at a discharge level, a second detector which is controlled by an enable signal for designating lower bit priority and detects whether a carry line portion on a lower bit side of the switch circuit is at a discharge level, and a third detector for detecting whether one of outputs from the first and second detectors and the operand input bit are both in an active state.
摘要翻译： 优先编码器包括编码器，用于编码由分别提供给编码器的位输入端的多个位，选择器组成的输入，用于分别接收操作数输入的多个位中的相应位，每个选择器包括 由操作数输入位控制的开关电路，与开关电路串联连接并与所有选择器串联连接的输送线，第一预充电电路，连接到开关的一端侧的输送线部分 电路，用于在预定定时对所述携带线进行预充电;第一检测器，其由用于指定高位优先级的使能信号控制，并且检测所述开关电路的上位端的运送线部分的电位是否处于放电 电平，第二检测器，其由用于指定较低位优先级的使能信号控制，并检测开关ci的较低位侧的进位线部分 电路处于放电电平，第三检测器检测来自第一和第二检测器的输出和操作数输入位之一是否处于活动状态。
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4.发明授权Semiconductor integrated circuit device comprising memory area in which structurally different memory cells are included 失效半导体集成电路器件包括其中包括结构不同的存储器单元的存储器区域
公开(公告)号：US5420817A
公开(公告)日：1995-05-30
申请号：US167152
申请日：1993-12-16
IPC分类号： G11C17/08 , G11C16/02 , G11C16/04 , G11C17/00 , G11C17/12 , H01L21/8247 , H01L27/115
CPC分类号： G11C17/12
摘要： The same bit lines are used in common to a fixed data cell array and a memory cell array. The output section of the fixed data cell array is connected to an output circuit, just like the output section of the memory cell array. In response to signal CON supplied from a computer, an array selector examines the states of the arrays and performs switching between the state where one of the arrays can be selected and the state where neither of them can be selected. In the case where an externally-programmable memory, such as an EPROM, is employed, a write control circuit operates with respect only to the memory cell array, and prohibits data from being written in the fixed data cell array. The fixed data cell array is pre-programmed as a nonvolatile memory by programming means different from that used for programming the cells of the memory cell array.
摘要翻译： 固定数据单元阵列和存储单元阵列共同使用相同的位线。 固定数据单元阵列的输出部分连接到输出电路，就像存储单元阵列的输出部分一样。 响应于从计算机提供的信号CON，数组选择器检查阵列的状态，并且在可以选择其中一个阵列的状态和不能选择它们的状态之间进行切换。 在采用诸如EPROM的外部可编程存储器的情况下，写入控制电路仅对存储单元阵列进行操作，并且禁止将数据写入固定数据单元阵列。 固定数据单元阵列通过与用于对存储单元阵列的单元进行编程的编程手段不同的编程手段，被预编程为非易失性存储器。
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公开(公告)号：US20110302657A1
公开(公告)日：2011-12-08
申请号：US13167821
申请日：2011-06-24
IPC分类号： G06F21/00
CPC分类号： G06F21/577 , H04L63/1441 , H04L63/20
摘要： In a security countermeasure function evaluation apparatus, an estimator operates an input unit, whereby an evaluation point calculation unit makes an evaluation as to whether each item of countermeasure information representing a security countermeasure function in detail satisfies each item of sufficient condition table information, and the evaluation point is calculated from the evaluation result of each item, whereby the transition probability calculation unit calculates a transition probability based on the evaluation point.
摘要翻译： 在安全对策功能评价装置中，估计器操作输入单元，由此评估点计算单元对表示安全对策功能的每个对策信息的每个项目是否详细满足每个充足条件表信息的项目进行评估，并且 根据各项目的评价结果计算评价点，由此，转移概率计算部基于评价点来计算转移概率。
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6.发明授权Arithmetic method and apparatus and crypto processing apparatus for performing multiple types of cryptography 失效用于执行多种类型的密码术的算术方法和装置以及密码处理装置公开(公告)号：US07277540B1
公开(公告)日：2007-10-02
申请号：US09487483
申请日：2000-01-19
申请人： Masue Shiba , Shinichi Kawamura
发明人： Masue Shiba , Shinichi Kawamura
摘要： An arithmetic apparatus for performing a long product-sum operation includes an integer unit arithmetic circuit, a finite field GF(2^m) based unit arithmetic circuit logically adjacent to the integer unit arithmetic circuit, a selector for selecting the integer unit arithmetic circuit or the finite field GF(2^m) based unit arithmetic circuit, and an adder circuit which has a buffer for storing interim result data, adds the interim result data to the result data obtained by one of the integer unit arithmetic circuit and the finite field GF(2^m) based unit arithmetic circuit which is selected by the selector, propagates a carry in an integer unit arithmetic operation, and propagates no carry in a finite field GF(2^m) based unit arithmetic operation.
摘要翻译： 用于执行长乘积和运算的运算装置包括整数单位运算电路，与整数单位运算电路逻辑相邻的基于有限域GF（2 ^ m）的单位运算电路，选择器，用于选择整数单位运算电路或 基于有限域GF（2 ^ m）的单位运算电路和具有用于存储中间结果数据的缓冲器的加法器电路，将中间结果数据与由整数单位运算电路和有限域中的一个获得的结果数据相加 由选择器选择的基于GF（2 ^ m）的单位运算电路以整数单位算术运算传播进位，并且在基于有限域GF（2 ^ m）的单位算术运算中不传播进位。
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公开(公告)号：US20050209970A1
公开(公告)日：2005-09-22
申请号：US11079204
申请日：2005-03-15
申请人： Masue Shiba , Koji Yura
发明人： Masue Shiba , Koji Yura
IPC分类号： G06F21/00 , H04K1/00 , H04N7/16 , H04N21/418 , H04N21/4623
CPC分类号： H04N21/4623 , G06F21/575 , H04N7/165
摘要： According to a first aspect of the present invention, a conditional-access program can be updated without replacing a conditional-access large scale integrated circuit (LSI) or a conditional-access terminal device main-body. A conditional-access terminal device reads and decrypts an encrypted conditional-access program from a memory storage device at start-up, and executes conditional-access processing in conformity to the obtained conditional-access program. Consequently, by replacing the memory storage device, the conditional-access program can be updated.
摘要翻译： 根据本发明的第一方面，可以更新条件访问程序而不替换条件访问大规模集成电路（LSI）或条件接入终端设备主体。 条件接收终端装置在启动时从存储器存储装置中读取和解密加密的条件访问程序，并且根据获得的条件访问程序执行条件访问处理。 因此，通过更换存储器装置，可以更新条件访问程序。
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