公开(公告)号：US07925866B2

公开(公告)日：2011-04-12

申请号：US12314095

申请日：2008-12-03

申请人： Peter Richard Greenhalgh ,  Andrew Christopher Rose ,  Simon John Craske ,  Max Zardini

发明人： Peter Richard Greenhalgh ,  Andrew Christopher Rose ,  Simon John Craske ,  Max Zardini

IPC分类号： G06F9/30

CPC分类号： G06F9/30185 ,  G06F9/30149 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3861

摘要： A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.

摘要翻译： 提供了一种用于处理由处理电路执行的指令的数据处理装置和方法。 处理电路具有多个处理器状态，每个处理器状态具有与其相关联的不同指令集。 预解码电路接收从存储器取出的指令，并执行预解码操作以产生相应的预解码指令，然后将那些预先解码的指令存储在高速缓存中以供处理电路访问。 预解码电路在假设处理器状态下执行预解码操作，并且高速缓存被配置为存储与预解码指令相关联的推测性处理器状态的指示。 如果处理电路的当前处理器状态与存储在该指令的高速缓存中的推测性处理器状态的指示相匹配，则处理电路然后被布置为仅使用来自高速缓存的相应的预解码指令来执行序列中的指令。 这提供了一种用于检测由于处理器状态的不正确假设而被预解码操作损坏的指令的简单而有效的机制。

公开(公告)号：US07925867B2

公开(公告)日：2011-04-12

申请号：US12458512

申请日：2009-07-14

申请人： Peter Richard Greenhalgh ,  Max Zardini ,  Allan John Skillman ,  Daniel Paul Schostak

发明人： Peter Richard Greenhalgh ,  Max Zardini ,  Allan John Skillman ,  Daniel Paul Schostak

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/3816 ,  G06F9/382

摘要： A data processing and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from a memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in the cache for access by the processing circuitry. If a pre-decoded instruction crosses a cache line boundary, then checking circuitry in respect of selected types of pre-decoded instruction checks for consistency between the first portion of the pre-decoded instruction stored within a first cache line and a contiguous second portion of the pre-decoded instruction stored within a second cache line. If this consistency check is passed such that the two portions are self-consistent, then the pre-decoded instruction can be further decoded and issued. If the consistency check is failed, or the pre-decoded instruction is not of a type for which consistency checking is supported, then re-generation of the pre-decoded instruction is triggered.

摘要翻译： 提供用于预解码指令的数据处理和方法。 数据处理装置具有用于接收从存储器取出的指令并用于执行预解码操作以产生相应的预解码指令的预解码电路，然后存储在缓存器中以供处理电路访问。 如果预解码指令跨越高速缓存线边界，则检查电路对所选择的预解码指令类型的类型进行检查，以确定存储在第一高速缓存行内的预解码指令的第一部分与第一高速缓存行的连续第二部分之间的一致性 所述预解码指令存储在第二高速缓存行内。 如果通过这种一致性检查使得两部分是自相一致的，则可以进一步解码和发出预解码指令。 如果一致性检查失败，或者预解码指令不是支持一致性检查的类型，则触发预解码指令的再生成。

公开(公告)号：US20100017580A1

公开(公告)日：2010-01-21

申请号：US12458512

申请日：2009-07-14

申请人： Peter Richard Greenhalgh ,  Max Zardini ,  Allan John Skillman ,  Daniel Paul Schostak

发明人： Peter Richard Greenhalgh ,  Max Zardini ,  Allan John Skillman ,  Daniel Paul Schostak

IPC分类号： G06F9/30 ,  G06F9/312

CPC分类号： G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/3816 ,  G06F9/382

摘要： A data processing and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from a memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in the cache for access by the processing circuitry. If a pre-decoded instruction crosses a cache line boundary, then checking circuitry in respect of selected types of pre-decoded instruction checks for consistency between the first portion of the pre-decoded instruction stored within a first cache line and a contiguous second portion of the pre-decoded instruction stored within a second cache line. If this consistency check is passed such that the two portions are self-consistent, then the pre-decoded instruction can be further decoded and issued. If the consistency check is failed, or the pre-decoded instruction is not of a type for which consistency checking is supported, then re-generation of the pre-decoded instruction is triggered.

摘要翻译： 提供用于预解码指令的数据处理和方法。 数据处理装置具有用于接收从存储器取出的指令并用于执行预解码操作以产生相应的预解码指令的预解码电路，然后存储在缓存器中以供处理电路访问。 如果预解码指令跨越高速缓存线边界，则检查电路对所选择类型的预解码指令检查，以确定存储在第一高速缓存行内的预解码指令的第一部分与第一高速缓存行的连续第二部分之间的一致性 所述预解码指令存储在第二高速缓存行内。 如果通过这种一致性检查使得两部分是自相一致的，则可以进一步解码和发出预解码指令。 如果一致性检查失败，或者预解码指令不是支持一致性检查的类型，则触发预解码指令的再生成。

公开(公告)号：US20090249033A1

公开(公告)日：2009-10-01

申请号：US12314095

申请日：2008-12-03

申请人： Peter Richard Greenhalgh ,  Andrew Christoper Rose ,  Simon John Craske ,  Max Zardini

发明人： Peter Richard Greenhalgh ,  Andrew Christoper Rose ,  Simon John Craske ,  Max Zardini

IPC分类号： G06F9/312 ,  G06F9/30 ,  G06F12/08

CPC分类号： G06F9/30185 ,  G06F9/30149 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3861

摘要： A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.

摘要翻译： 提供了一种用于处理由处理电路执行的指令的数据处理装置和方法。 处理电路具有多个处理器状态，每个处理器状态具有与其相关联的不同指令集。 预解码电路接收从存储器取出的指令，并执行预解码操作以产生相应的预解码指令，然后将那些预先解码的指令存储在高速缓存中以供处理电路访问。 预解码电路在假设处理器状态下执行预解码操作，并且高速缓存被配置为存储与预解码指令相关联的推测性处理器状态的指示。 如果处理电路的当前处理器状态与存储在该指令的高速缓存中的推测性处理器状态的指示相匹配，则处理电路然后被布置为仅使用来自高速缓存的相应的预解码指令来执行序列中的指令。 这提供了一种用于检测由于处理器状态的不正确假设而被预解码操作损坏的指令的简单而有效的机制。