摘要:
In response to a transfer stimulus, performance of a processing workload is transferred from a source processing circuitry to a destination processing circuitry, in preparation for the source processing circuitry to be placed in a power saving condition following the transfer. To reduce the number of memory fetches required by the destination processing circuitry following the transfer, a cache of the source processing circuitry is maintained in a powered state for a snooping period. During the snooping period, cache snooping circuitry snoops data values in the source cache and retrieves the snoop data values for the destination processing circuitry.
摘要:
A data processing apparatus and method are provided for switching performance of a workload between two processing circuits. The data processing apparatus has first processing circuitry which is architecturally compatible with second processing circuitry, but with the first processing circuitry being micro-architecturally different from the second processing circuitry. At any point in time, a workload consisting of at least one application and at least one operating system for running that application is performed by one of the first processing circuitry and the second processing circuitry. A switch controller is responsive to a transfer stimulus to perform a handover operation to transfer performance of the workload from source processing circuitry to destination processing circuitry, with the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry. During the handover operation, the switch controller causes the source processing circuitry to makes it current architectural state available to the destination processing circuitry, the current architectural state being that state not available from shared memory at a time the handover operation is initiated, and that is necessary for the destination processing circuitry to successfully take over performance of the workload from the source processing circuitry. In addition, the switch controller masks predetermined processor specific configuration information from the at least one operating system such that the transfer of the workload is transparent to that operating system. Such an approach has been found to yield significant energy consumption benefits whilst avoiding complexities associated with providing operating systems with the capability for switching applications between processing circuits.
摘要:
The present invention provides a data processing apparatus comprising processing circuitry for executing a sequence of instructions and pre-decoding circuitry for receiving the instructions fetched from memory. The pre-decoding circuitry performs a pre-decoding operation to generate corresponding pre-decoded instructions and stores them in a cache for access by the processing circuitry. For each instruction fetched from the memory, the pre-decoding circuitry detects whether the instruction is an abnormal instruction and upon such detection provides in association with a corresponding pre-decoded instruction an identifier identifying that instruction as abnormal.
摘要:
A data processing apparatus is provided with pre-decoding circuitry 10 serving to generate pre-decoded instructions which are stored within an instruction cache 20. The pre-decoded instructions from the instruction cache 20 are read by decoding circuitry 45, 50, 46 and used to form control signals for controlling processing operations corresponding to the pre-decoded instructions. The program instructions originally fetched can belong to respective ones of a plurality of instruction sets. Instructions from one instruction set are pre-decoded by the pre-decoding circuitry 10 into pre-decoded instructions having a shared format to represent shared functionality with corresponding instructions taken from another of the instruction sets. In this way, a shared portion of the decoding circuitry can generate control signals with respect to the shared functionality of instructions from both of these different instruction sets.
摘要:
A data processing apparatus and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in a cache for access by processing circuitry. For a first set of instructions, each instruction comprises a plurality of instruction portions, and the pre-decoding circuitry generates a corresponding pre-decoded instruction comprising a plurality of pre-decoded instruction portions. If when applying the pre-decoding operation to an instruction in the first set, the pre-decoding circuitry does not have access to all of the plurality of instruction portions of that instruction, the pre-decoding circuitry is arranged to provide in association with at least one pre-decoded instruction portion that it does generate, an indication that the pre-decoded instruction portion relates to an incomplete pre-decoding operation. This provides a simple and effective mechanism for detecting situations where a pre-decoded instruction as later read from the cache may have become corrupted by the pre-decoding operation, and accordingly should not be relied upon.
摘要:
A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.
摘要:
In a data processing system, data representing program instructions is fetched from memory, each instruction being from one of a plurality of sets of instructions including at least first and second sets of instructions and each program instruction within the fetched data comprising one or more blocks to be pre-decoded, each block representing a portion of an instruction. Pre-decoding circuitry is configured to perform pre-decoding operations on the blocks. For at least one portion of an instruction from the first set of instructions and at least one portion of an instruction from the second set of instructions the pre-decoding operation performed on a block fetched from memory is independent of whether the block is identified as representing the at least one portion of an instruction from the first set of instructions or as the at least one portion of an instruction from the second set of instructions.
摘要:
A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.
摘要:
A data processing apparatus has first processing circuitry which is architecturally compatible with second processing circuitry, but with the first processing circuitry being miero-architccturally different from the second processing circuitry. A switch controller performs a handover operation to transfer performance of the workload from source processing circuitry to destination processing circuitry, with the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry. During the handover operation, the switch controller causes the source processing circuitry to makes it current architectural state available to the destination processing circuitry and is necessary for the destination processing circuitry to successfully lake over performance of the workload from the source processing circuitry. The switch controller masks predetermined processor specific configuration information such that the transfer of the workload is transparent to that operating system.
摘要:
The present invention provides a data processing apparatus comprising processing circuitry for executing a sequence of instructions and pre-decoding circuitry for receiving the instructions fetched from memory. The pre-decoding circuitry performs a pre-decoding operation to generate corresponding pre-decoded instructions and stores them in a cache for access by the processing circuitry. For each instruction fetched from the memory, the pre-decoding circuitry detects whether the instruction is an abnormal instruction and upon such detection provides in association with a corresponding pre-decoded instruction an identifier identifying that instruction as abnormal.