公开(公告)号：US08780171B2

公开(公告)日：2014-07-15

申请号：US12970302

申请日：2010-12-16

申请人： Koji Kamiya ,  Mayuki Hashi ,  Kinichi Ootsu

发明人： Koji Kamiya ,  Mayuki Hashi ,  Kinichi Ootsu

IPC分类号： H04N13/00

CPC分类号： H04N13/178 ,  H04N13/139 ,  H04N13/161 ,  H04N13/194 ,  H04N13/239

摘要： Disclosed herein is a video signal processor including: a combining process section adapted to superimpose a first marker signal on a first video signal component at a specific position and superimpose a second marker signal on a second video signal component at roughly the same position as the specific position; and a control section adapted to control the condition of superimposition of the first and second marker signals so that an image appears to indicate that the first and second marker signals are combined correctly when the first and second video signal components are combined in a correct phase relationship, and so that an image appears to indicate that the first and second marker signals are combined incorrectly if the first and second video signal components are combined in an incorrect phase relationship.

摘要翻译： 本文公开了一种视频信号处理器，包括：组合处理部分，适于将第一标记信号叠加在特定位置的第一视频信号分量上，并将第二标记信号叠加在与特定的位置大致相同位置的第二视频信号分量上 位置; 以及控制部分，适于控制第一和第二标记信号的叠加条件，使得当第一和第二视频信号分量以正确的相位关系组合时，图像看起来表明第一和第二标记信号被正确组合 并且使得如果第一和第二视频信号分量以不正确的相位关系组合，则图像看起来表明第一和第二标记信号被不正确地组合。

公开(公告)号：US06570618B1

公开(公告)日：2003-05-27

申请号：US09190462

申请日：1998-11-13

申请人： Mayuki Hashi

发明人： Mayuki Hashi

IPC分类号： H04N314

CPC分类号： H04N5/235 ,  H04N5/335

摘要： When the reset gate electrode of the charge detecting section is driven with the reset pulse of three levels, it is difficult to realize the timing control when high speed operation is required. In the charge detecting section of the CCD solid-state image sensing apparatus having wide dynamic range, two reset gate electrodes, for example, are arranged in vertical between the FD area and RD area, and different reset pulses &phgr;RG1, &phgr;RG2 are applied to these reset gate electrodes to realize the reset operation, clipping operation and adding operation through the driving by the 2-level pulse.

摘要翻译： 当电荷检测部分的复位栅电极以三电平的复位脉冲驱动时，在需要高速运行时难以实现定时控制。 在具有宽动态范围的CCD固体摄像装置的电荷检测部分中，例如在FD区域和RD区域之间垂直布置两个复位栅电极，并且将这些复位脉冲phiRG1，phiRG2应用于这些 复位栅电极通过2电平脉冲的驱动实现复位操作，削波操作和相加操作。

公开(公告)号：US20110149023A1

公开(公告)日：2011-06-23

申请号：US12970302

申请日：2010-12-16

申请人： Koji Kamiya ,  Mayuki Hashi ,  Kinichi Ootsu

发明人： Koji Kamiya ,  Mayuki Hashi ,  Kinichi Ootsu

IPC分类号： H04N13/00

CPC分类号： H04N13/178 ,  H04N13/139 ,  H04N13/161 ,  H04N13/194 ,  H04N13/239

摘要： Disclosed herein is a video signal processor including: a combining process section adapted to superimpose a first marker signal on a first video signal component at a specific position and superimpose a second marker signal on a second video signal component at roughly the same position as the specific position; and a control section adapted to control the condition of superimposition of the first and second marker signals so that an image appears to indicate that the first and second marker signals are combined correctly when the first and second video signal components are combined in a correct phase relationship, and so that an image appears to indicate that the first and second marker signals are combined incorrectly if the first and second video signal components are combined in an incorrect phase relationship.

摘要翻译： 本文公开了一种视频信号处理器，包括：组合处理部分，适于将第一标记信号叠加在特定位置的第一视频信号分量上，并将第二标记信号叠加在与特定的位置大致相同位置的第二视频信号分量上 位置; 以及控制部分，适于控制第一和第二标记信号的叠加条件，使得当第一和第二视频信号分量以正确的相位关系组合时，图像看起来表明第一和第二标记信号被正确组合 并且使得如果第一和第二视频信号分量以不正确的相位关系组合，则图像看起来表明第一和第二标记信号被不正确地组合。

公开(公告)号：US09077841B2

公开(公告)日：2015-07-07

申请号：US13434986

申请日：2012-03-30

申请人： Mayuki Hashi ,  Koji Kamiya ,  Kiyoshi Yamauchi

发明人： Mayuki Hashi ,  Koji Kamiya ,  Kiyoshi Yamauchi

IPC分类号： H04N7/01 ,  H04N21/236

CPC分类号： H04N7/012 ,  H04N21/23602

摘要： There is provided a video processing apparatus including a video addition unit for receiving two systems of input interlaced video signals each including two fields, and adding the video signals to generate a ½× video signal of the input interlaced video signal. The video addition unit adds a second field of the interlaced video signal of one system among the two systems and a first field of the interlaced video signal of the other system to generate the ½× video signal of the input interlaced video signal, subjects the interlaced video signal of the other system to 1 horizontal line delay when the ½× video signal is generated, validates a horizontal line in a vertical blanking interval on one row of a top line of valid lines in the first field of the interlaced video signal of the other system, and then adds the video signals of the two systems.

摘要翻译： 提供了一种视频处理装置，包括：视频添加单元，用于接收每个包括两个场的两个输入隔行扫描视频信号，并且相加视频信号以产生输入的隔行视频信号的1/2像素视频信号。 视频添加单元在两个系统之间添加一个系统的隔行视频信号的第二场和另一个系统的隔行扫描视频信号的第一场，以产生输入隔行视频信号的1/2像素视频信号，使隔行扫描 视频信号在1/2视频信号生成时为1条水平行延迟，在该隔行扫描视频信号的第一场中的有效行的顶行一行的垂直消隐间隔中验证水平线 其他系统，然后添加两个系统的视频信号。

公开(公告)号：US20120257106A1

公开(公告)日：2012-10-11

申请号：US13434986

申请日：2012-03-30

申请人： Mayuki HASHI ,  Koji KAMIYA ,  Kiyoshi YAMAUCHI

发明人： Mayuki HASHI ,  Koji KAMIYA ,  Kiyoshi YAMAUCHI

IPC分类号： H04N7/01

CPC分类号： H04N7/012 ,  H04N21/23602

摘要： There is provided a video processing apparatus including a video addition unit for receiving two systems of input interlaced video signals each including two fields, and adding the video signals to generate a ½x video signal of the input interlaced video signal. The video addition unit adds a second field of the interlaced video signal of one system among the two systems and a first field of the interlaced video signal of the other system to generate the ½x video signal of the input interlaced video signal, subjects the interlaced video signal of the other system to 1 horizontal line delay when the ½x video signal is generated, validates a horizontal line in a vertical blanking interval on one row of a top line of valid lines in the first field of the interlaced video signal of the other system, and then adds the video signals of the two systems.

摘要翻译： 提供了一种视频处理装置，包括：视频添加单元，用于接收每个包括两个场的两个输入隔行扫描视频信号，并且加上视频信号以产生输入的隔行视频信号的1/2视频信号。 视频添加单元在两个系统之间添加一个系统的隔行视频信号的第二场和另一个系统的隔行视频信号的第一场，以产生输入的隔行视频信号的1/2视频信号，对隔行视频 当生成1/2视频信号时，其他系统的信号为1水平行延迟，在另一个系统的隔行扫描视频信号的第一场中的有效行的顶行的一行的垂直消隐间隔中的垂直消隐间隔中验证水平线 ，然后添加两个系统的视频信号。