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1.发明授权Simplified least-recently-used entry replacement in associative cache memories and translation lookaside buffers 失效关联高速缓冲存储器和翻译后备缓冲区中简化的最近最近使用的条目替换
公开(公告)号：US5802568A
公开(公告)日：1998-09-01
申请号：US660090
申请日：1996-06-06
CPC分类号： G06F12/123 , G06F2212/684
摘要： A simplified or pseudo least-recently-used (LRU) process and circuit in a cache memory or translation lookaside table (TLB) maintains status bits to identify which entries are valid and which entries have been recently used. If none of the entries are invalid, only entries not indicated as recently used are replaced (or overwritten). When all entries are indicated as valid and recently used, status bits other than the status bits for the entry last accessed are changed to indicate that the corresponding entries have not been recently used. Accordingly, those entries can be replaced, but the most recently used entry still cannot be replaced. This makes the pseudo LRU process closer to a full LRU process when compared to pseudo LRU processes which clear all status bits simultaneously. Complexity for the LRU process is not greatly increased because the address generated for the most recent access of an entry can be used to identify the bit which is not changed.
摘要翻译： 高速缓存或翻译后视表（TLB）中的简化或伪最近最近使用（LRU）过程和电路维护状态位，以识别哪些条目有效以及哪些条目最近被使用。 如果没有条目无效，则仅替换（或覆盖）最近使用的条目。 当所有条目被指示为有效和最近使用时，更改上一次访问的条目的状态位以外的状态位，以指示相应的条目尚未被最近使用。 因此，这些条目可以被替换，但是最近使用的条目仍然不能被替换。 当与同时清除所有状态位的伪LRU进程相比时，伪LRU进程更接近完整的LRU进程。 LRU过程的复杂性并不会大大增加，因为为条目的最新访问生成的地址可用于识别未更改的位。
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2.发明授权DMA transfer method for a system including a single-chip processor with a processing core and a device interface in different clock domains 有权包括具有处理核心的单芯片处理器和不同时钟域中的器件接口的系统的DMA传输方法公开(公告)号：US06553435B1
公开(公告)日：2003-04-22
申请号：US09229013
申请日：1999-01-12
申请人： Kevin B. Normoyle , Michael A. Csoppenszky , Jaybharat Boddu , Jui-Cheng Su , Alex S. Han , Rajasekhar Cherabuddi , Tzungren Tzeng
发明人： Kevin B. Normoyle , Michael A. Csoppenszky , Jaybharat Boddu , Jui-Cheng Su , Alex S. Han , Rajasekhar Cherabuddi , Tzungren Tzeng
IPC分类号： G06F1328
CPC分类号： G06F12/0897 , G06F12/0888 , G06F12/1054 , G06F12/1081 , G06F13/28 , G06F15/7832
摘要： A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing core. An internal communications protocol uses synchronizers and data buffers to transfer information between a clock domain of the processing core and a clock domain of the I/O system. The synchronizers transfer control and handshake signal between clock domains, but the data buffer transfers data without input or output synchronization circuitry for data bits. Throughput for the system is high because the processing unit has direct access to I/O system so that no delays are incurred for complex mechanisms which are commonly employed between a CPU and an external I/O chip-set. Throughput is further increased by holding data from one DMA transfer in the data buffer for use in a subsequent DMA transfer. In one embodiment, the integrated I/O system contains a dedicated memory management unit including a translation lookaside buffer which converts I/O addresses to physical addresses for the processing core.
摘要翻译： 单芯片中央处理单元（CPU）包括处理核心和与处理核心异步运行的完整高速缓存相干I / O系统。 内部通信协议使用同步器和数据缓冲器在处理核心的时钟域和I / O系统的时钟域之间传输信息。 同步器在时钟域之间传送控制和握手信号，但是数据缓冲器传输数据，而不需要输入或输出同步电路来进行数据位。 系统的吞吐量很高，因为处理单元可以直接访问I / O系统，以便在CPU和外部I / O芯片组之间通常采用的复杂机制不会产生延迟。 通过保存来自数据缓冲器中的一个DMA传输的数据以进行后续DMA传输来进一步增加吞吐量。 在一个实施例中，集成I / O系统包含专用存储器管理单元，其包括将I / O地址转换为处理核的物理地址的翻译后备缓冲器。
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3.发明授权Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor 失效用于单芯片处理器的低延迟，高吞吐量的集成缓存一致I / O系统
公开(公告)号：US5884100A
公开(公告)日：1999-03-16
申请号：US660026
申请日：1996-06-06
申请人： Kevin B. Normoyle , Michael A. Csoppenszky , Jaybharat Boddu , Jui-Cheng Su , Alex S. Han , Rajasekhar Cherabuddi , Tzungren Tzeng
发明人： Kevin B. Normoyle , Michael A. Csoppenszky , Jaybharat Boddu , Jui-Cheng Su , Alex S. Han , Rajasekhar Cherabuddi , Tzungren Tzeng
CPC分类号： G06F12/0897 , G06F12/1081 , G06F13/28 , G06F15/7832 , G06F12/0888 , G06F12/1054
摘要： A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing core. An internal communications protocol uses synchronizers and data buffers to transfer information between a clock domain of the processing core and a clock domain of the I/O system. The synchronizers transfer control and handshake signal between clock domains, but the data buffer transfers data without input or output synchronization circuitry for data bits. Throughput for the system is high because the processing unit has direct access to I/O system so that no delays are incurred for complex mechanisms which are commonly employed between a CPU and an external I/O chip-set. Throughput is further increased by holding data from one DMA transfer in the data buffer for use in a subsequent DMA transfer. In one embodiment, the integrated I/O system contains a dedicated memory management unit including a translation lookaside buffer which converts I/O addresses to physical addresses for the processing core.
摘要翻译： 单芯片中央处理单元（CPU）包括处理核心和与处理核心异步运行的完整高速缓存相干I / O系统。 内部通信协议使用同步器和数据缓冲器在处理核心的时钟域和I / O系统的时钟域之间传输信息。 同步器在时钟域之间传送控制和握手信号，但是数据缓冲器传输数据，而不需要输入或输出同步电路来进行数据位。 系统的吞吐量很高，因为处理单元可以直接访问I / O系统，以便在CPU和外部I / O芯片组之间通常采用的复杂机制不会产生延迟。 通过保存来自数据缓冲器中的一个DMA传输的数据以进行后续DMA传输来进一步增加吞吐量。 在一个实施例中，集成I / O系统包含专用存储器管理单元，其包括将I / O地址转换为处理核的物理地址的翻译后备缓冲器。
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公开(公告)号：US5987081A
公开(公告)日：1999-11-16
申请号：US884253
申请日：1997-06-27
CPC分类号： G06F5/06 , H04L7/0012 , H04L7/02 , H04L7/0004
摘要： A synchronizer comprised in part of a series of flip-flops is used to deterministically transfer data between clock domains during system test. Flip-flops in the clock domain operating at a higher clock frequency have a clock enable signal. The clock enable signal is defined so as to approximately align the enabled rising clock edges of the faster clock signal with the falling edges of the slower clock signal. This approximate alignment provides a timing window of one half period of the slower clock for the data to stabilize at the input of a flip-flop in the faster clock domain before it is sampled. This ensures deterministic transfer of data. Data flow control circuitry can be used to provide a ready signal to the faster clock domain to indicate that the synchronizer is available to transfer a synchronization signal. After testing is complete, the synchronizer can operate in an application mode wherein one or more of the clock enable signals is set to a continuous high level to minimize latency.
摘要翻译： 在系统测试期间，使用包括在一系列触发器中的同步器来确定性地在时钟域之间传送数据。 在较高时钟频率下操作的时钟域中的触发器具有时钟使能信号。 时钟使能信号被定义为使得较快时钟信号的使能的上升时钟沿与较慢时钟信号的下降沿近似对准。 这种近似对准提供了较慢时钟的一个半周期的定时窗口，以便数据在采样之前在更快的时钟域中稳定在触发器的输入端。 这确保数据的确定性传输。 数据流控制电路可用于向较快的时钟域提供就绪信号，以指示同步器可用于传送同步信号。 测试完成后，同步器可以以应用模式工作，其中一个或多个时钟使能信号被设置为连续的高电平以最小化等待时间。
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5.发明授权Structure and method for bi-directional data transfer between asynchronous clock domains 失效异步时钟域之间双向数据传输的结构和方法
公开(公告)号：US5852608A
公开(公告)日：1998-12-22
申请号：US659729
申请日：1996-06-06
CPC分类号： G06F5/065
摘要： Bi-directional data transfers between a first system and a second system, which have asynchronous clock domains, are performed using a single dual-port memory. A direction control circuit, which is connected between the first and second systems, determines the desired direction of data transfer and generates one or more direction signals representative of this direction. A write control circuit is coupled to receive a direction control signal, as well as write control signals from the first and second systems. Similarly, a read control signal is coupled to receive a direction control signal, as well as read control signals from the first and second systems. If data transfer is to proceed from the first system to the second system, the write control circuit gives the first system control over the write port of the dual-port memory, and the read control circuit gives the second system control over the read port of the dual-port memory in response to the direction control signals. Conversely, if data transfer is to proceed from the second system to the first system, the write control circuit gives the second system control over the write port of the dual-port memory, and the read control circuit gives the first system control over the read port of the dual-port memory in response to the direction control signals.
摘要翻译： 具有异步时钟域的第一系统和第二系统之间的双向数据传输使用单个双端口存储器执行。 连接在第一和第二系统之间的方向控制电路确定期望的数据传送方向，并产生代表该方向的一个或多个方向信号。 写入控制电路被耦合以接收方向控制信号，以及来自第一和第二系统的写入控制信号。 类似地，读控制信号被耦合以接收方向控制信号，以及从第一和第二系统读取控制信号。 如果从第一系统进行数据传输到第二系统，则写入控制电路对双端口存储器的写入端口进行第一系统控制，并且读取控制电路对第二系统的读取端口进行第二系统控制 响应方向控制信号的双端口存储器。 相反，如果数据传输从第二系统进行到第一系统，则写入控制电路对双端口存储器的写入端口进行第二系统控制，并且读取控制电路对读取的第一系统进行控制 端口的双端口存储器响应方向控制信号。
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6.发明授权Predictive status flag generation in a first-in first-out (FIFO) memory device method and apparatus 失效先进先出（FIFO）存储器件方法和装置中的预测状态标志生成
公开(公告)号：US5506809A
公开(公告)日：1996-04-09
申请号：US268170
申请日：1994-06-29
CPC分类号： G06F5/12 , G06F2205/102 , G06F2205/126
摘要： Method and apparatus are described for generating more accurate and timely FIFO status flags. Preferably, the asynchronous FIFO read and write pointers are conventionally compared with one another and the output of such comparison is glitch-suppressed. During such operation in accordance with the invented method and apparatus, prediction signals are used to precondition the status flag output latches so that they will provide the earliest possible accurate status reflecting asynchronous read and write clock activity. If a boundary condition is present--e.g. depending upon the next read or write clock activity, the FIFO's half full status flag may change where such change is impossible to predict because it is unknowable whether the next operation will be a read or a write or both--then an asynchronous state machine takes over from the prediction flag logic to ensure accurate and early preconditioning of the status flags' output latches. When no such boundary condition is present, the state machine is dormant and the prediction logic is active.
摘要翻译： 描述了用于生成更准确和及时的FIFO状态标志的方法和装置。 优选地，异步FIFO读和写指针通常彼此进行比较，并且这种比较的输出被毛刺抑制。 在根据本发明的方法和装置的这种操作期间，使用预测信号来预处理状态标志输出锁存器，使得它们将提供反映异步读和写时钟活动的最早可能的准确状态。 如果存在边界条件 - 例如 取决于下一个读或写时钟活动，FIFO的半满状态标志可能会改变这种改变是不可能预测的，因为下一个操作是读还是写还是两者都是不可知的 - 那么异步状态机接管 从预测标志逻辑，以确保状态标志的输出锁存器的准确和早期预处理。 当没有这样的边界条件时，状态机是休眠的，并且预测逻辑是有效的。
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