公开(公告)号：US6162711A

公开(公告)日：2000-12-19

申请号：US232114

申请日：1999-01-15

申请人： Yi Ma ,  Stefanie Chaplin ,  Stephen Carl Kuehne ,  Brittin Charles Kane ,  Michael A. Laughery

发明人： Yi Ma ,  Stefanie Chaplin ,  Stephen Carl Kuehne ,  Brittin Charles Kane ,  Michael A. Laughery

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/20

CPC分类号： H01L21/28035 ,  H01L21/8238

摘要： A method and structure providing a dual layer silicon gate film having a uniform boron distribution therein and an ordered, uniform grain structure. Rapid thermal annealing is used to cause the diffusion of boron from an originally doped film to an originally undoped film, resulting in a uniform boron distribution within the structure, thereby rendering the structure resistant to vertical and lateral diffusion of the boron during subsequent processing at elevated temperatures.

摘要翻译： 提供其中具有均匀硼分布的双层硅栅极膜和有序的均匀晶粒结构的方法和结构。 使用快速热退火来使硼从原始掺杂的膜扩散到最初未掺杂的膜，导致在结构内形成均匀的硼分布，从而使结构在随后的高温处理期间对硼的垂直和横向扩散具有抗性 温度。

公开(公告)号：US06177363B1

公开(公告)日：2001-01-23

申请号：US09162542

申请日：1998-09-29

申请人： Pradip K. Roy ,  Yi Ma ,  Michael A. Laughery

发明人： Pradip K. Roy ,  Yi Ma ,  Michael A. Laughery

IPC分类号： H01L21336

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/3145 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/518

摘要： A method for forming a gate dielectric for use in ultra-thin integrated circuit environments includes forming a nitride layer under conditions effective to introduce defects in the nitride layer. The nitride layer is formed so as to have a defect density which is sufficiently large to provide a low interfacial trap density, particularly after annealing, and thus eliminate the charge trap problems associated with traditional nitride layers. This nitride layer can be used in, for example, ON or ONO structures, which can themselves be employed as a gate dielectric. The ON and ONO structures are preferably formed under low temperature and low pressure conditions to more effectively control oxide and nitride formation. This allows for the formation of gate dielectrics that are less than 10 nm in thickness. Moreover, these ultra-thin dielectrics can be formed in a single furnace cluster.

摘要翻译： 用于形成用于超薄集成电路环境的栅极电介质的方法包括在有效地在氮化物层中引入缺陷的条件下形成氮化物层。 氮化物层形成为具有足够大的缺陷密度以提供低的界面陷阱密度，特别是在退火之后，因此消除了与传统氮化物层相关的电荷陷阱问题。 该氮化物层可用于例如ON或ONO结构，其本身可用作栅极电介质。 ON和ONO结构优选在低温和低压条件下形成，以更有效地控制氧化物和氮化物的形成。 这允许形成厚度小于10nm的栅极电介质。 此外，这些超薄电介质可以形成在单个炉簇中。

公开(公告)号：US06440829B1

公开(公告)日：2002-08-27

申请号：US09223354

申请日：1998-12-30

申请人： Pradip K. Roy ,  Yi Ma ,  Michael A. Laughery

发明人： Pradip K. Roy ,  Yi Ma ,  Michael A. Laughery

IPC分类号： H01L213205

CPC分类号： H01L29/4925 ,  H01L21/28176 ,  H01L21/28211

摘要： A method and structure providing N-profile engineering at the poly/gate oxide and gate oxide/Si interfaces of a layered polysilicon/amorphous silicon structure of a semiconductor device. NH3 annealing provides for the introduction of nitrogen to the interface, where the nitrogen suppresses Boron diffusion, improves gate oxide integrity, and reduces the sites available for trapping hot carriers which degrade device performance.

摘要翻译： 在半导体器件的分层多晶硅/非晶硅结构的多晶硅/栅极氧化物和栅极氧化物/ Si界面处提供N型构造的方法和结构。 NH3退火提供了将氮引入界面，其中氮抑制硼扩散，提高了栅极氧化物的完整性，并且减少了用于捕获热载流子的位置，这降低了器件性能。