公开(公告)号：US5917215A

公开(公告)日：1999-06-29

申请号：US148555

申请日：1998-09-04

申请人： Kuen-Joung Chuang ,  Ming-Chih Chung ,  Jyh-Feng Lin

发明人： Kuen-Joung Chuang ,  Ming-Chih Chung ,  Jyh-Feng Lin

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： The present invention provides a structure and a method of forming a stepped trench oxide structure for a semiconductor memory device. The stepped trench oxide structure has "oxide steps" (e.g., 252 or 34A, 34B, 34C) in the gate oxide 20 surrounding the tunnel oxide layer 30. The oxide steps 34 are formed where the oxide thinning effect normally thins the tunnel oxide 30 around the perimeter of the tunnel oxide layer 30. The oxide steps 34 252 compensate for the oxide thinning effect and eliminate the problems associated with the oxide thinning effects. The oxide steps are preferably formed using one photo mask to form two different sized openings using different photoresist exposure times. The preferred method comprises forming a first tunneling opening 220A in a first (gate) oxide layer 220. Then, forming a second oxide layer 250 over said exposed substrate and said first oxide layer 220. A second opening 250A (smaller than the first opening) is formed in the second oxide layer thereby forming a first step 252. Next, a third oxide layer 270 is formed over said exposed substrate, the first oxide layer 220 and the second oxide layer 250 thereby propagating the first step 252. The oxide thinning edge effect is eliminated by the first step.

摘要翻译： 本发明提供一种形成用于半导体存储器件的阶梯状沟槽氧化物结构的结构和方法。 阶梯状沟槽氧化物结构在围绕隧道氧化物层30的栅极氧化物20中具有“氧化物步骤”（例如，252或34A，34B，34C）。形成氧化物步骤34，其中氧化物稀化效应通常使隧道氧化物30沉降 围绕隧道氧化物层30的周边。氧化物步骤34 252补偿氧化物稀化效应并消除与氧化物稀化效应相关的问题。 氧化物步骤优选使用一个光掩模形成，以使用不同的光致抗蚀剂曝光时间形成两个不同尺寸的开口。 优选的方法包括在第一（栅极）氧化物层220中形成第一隧道开口220A。然后，在所述暴露的衬底和所述第一氧化物层220上形成第二氧化物层250.第二开口250A（小于第一开口） 形成在第二氧化物层中，从而形成第一步骤252.接下来，在所述暴露的基板上形成第三氧化物层270，第一氧化物层220和第二氧化物层250由此传播第一步骤252.氧化物变薄边缘 效果通过第一步消除。

公开(公告)号：US5698466A

公开(公告)日：1997-12-16

申请号：US767016

申请日：1996-12-16

申请人： Hon-Shung Lui ,  Ming-Chih Chung ,  Shun-Hsiang Chen

发明人： Hon-Shung Lui ,  Ming-Chih Chung ,  Shun-Hsiang Chen

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L23/485 ,  H01L21/283

CPC分类号： H01L21/02164 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/31625 ,  H01L21/76816 ,  H01L23/485 ,  H01L2924/0002

摘要： A method of forming a tunnel-free tungsten plug is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer of borophospho-tetraethoxysilane (BP-TEOS) is deposited overlying the semiconductor device structures. Contact openings are etched through the insulating layer to the underlying semiconductor device structures wherein a tunnel opens in the insulating layer between contact openings. The semiconductor substrate is covered with a first barrier metal layer. The semiconductor substrate is coated with a spin-on-glass layer wherein the contact openings and the tunnel are filled with the spin-on-glass. The spin-on-glass is anisotropically etched away whereby the spin-on-glass remains only within the tunnel. The semiconductor substrate is covered with a second barrier metal layer. The contact openings are filled with tungsten which is etched back to form tungsten plugs within the contact openings wherein the filled tunnel provides tunnel-free tungsten plugs in the fabrication of the integrated circuit device.

摘要翻译： 描述形成无隧道钨塞的方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 沉积在半导体器件结构上的硼磷硅烷 - 四乙氧基硅烷（BP-TEOS）的绝缘层。 接触开口通过绝缘层蚀刻到下面的半导体器件结构，其中隧道在接触开口之间的绝缘层中开口。 半导体衬底被第一阻挡金属层覆盖。 半导体衬底涂覆有旋涂玻璃层，其中接触开口和隧道用旋涂玻璃填充。 旋涂玻璃被各向异性地蚀刻掉，因此旋涂玻璃仅保留在隧道内。 半导体衬底被第二阻挡金属层覆盖。 接触开口填充有钨，其被回蚀以在接触开口内形成钨塞，其中填充的隧道在集成电路器件的制造中提供无隧道的钨插塞。

公开(公告)号：US5726932A

公开(公告)日：1998-03-10

申请号：US663577

申请日：1996-06-13

申请人： Jin-Yuan Lee ,  Jenn-Ming Huang ,  Ming-Chih Chung

发明人： Jin-Yuan Lee ,  Jenn-Ming Huang ,  Ming-Chih Chung

IPC分类号： G11C11/412 ,  H01L27/11 ,  G11C11/00

CPC分类号： G11C11/412 ,  H01L27/1112 ,  Y10S257/903

摘要： An SRAM transistor cell on a doped semiconductor substrate comprises a first pass transistor and a second pass transistor, a first driver transistor and a second driver transistor and a saturated mode transistor. The device includes a first and second load resistor, first second and third nodes, a bit lines and interconnection lines. The first driver transistor drain region is connects to the first node. The control gate electrode cross connects via the first interconnection line to the second node. The second driver transistor drain region connects to the third node and the control gate electrode cross connects via the second interconnection line to the first node. The control gate electrodes of the pass transistors connect to a single input line. The drain region of the first pass transistor connects to the first node. The drain region of the second pass transistor connects to the second node. The source region of the first pass transistor connect to the bit line bar. The source region of the second pass transistor is connects to the bit line. The drain region and control gate electrode of the saturated mode transistor connect to the second node and the source region of the saturated mode transistor connects to the third node.

摘要翻译： 掺杂半导体衬底上的SRAM晶体管单元包括第一传输晶体管和第二传输晶体管，第一驱动晶体管和第二驱动晶体管以及饱和模式晶体管。 该器件包括第一和第二负载电阻器，第一和第三节点，位线和互连线。 第一驱动晶体管漏区连接到第一节点。 控制栅电极经由第一互连线交叉连接到第二节点。 第二驱动器晶体管漏极区域连接到第三节点，并且控制栅极电极经由第二互连线交叉连接到第一节点。 传输晶体管的控制栅电极连接到单个输入线。 第一级晶体管的漏极区连接到第一节点。 第二传输晶体管的漏极区域连接到第二节点。 第一级晶体管的源极区域连接到位线条。 第二传输晶体管的源极区域连接到位线。 饱和模式晶体管的漏极区域和控制栅电极连接到第二节点，饱和模式晶体管的源极区域连接到第三个节点。

公开(公告)号：US20080142675A1

公开(公告)日：2008-06-19

申请号：US11610708

申请日：2006-12-14

申请人： Kun-Yen Lu ,  Ming-Chih Chung

发明人： Kun-Yen Lu ,  Ming-Chih Chung

IPC分类号： F16M11/00

CPC分类号： F16M11/14 ,  F16M11/22 ,  F16M13/00 ,  Y10S248/917

摘要： A fastening apparatus and a holding rack which includes a holding dock, a holding device and the fastening apparatus. The holding device has a holding bracket and a fastened member. The fastening apparatus includes a collet and a sleeve. The collet has a bottom and a plurality of jutting plates. The collet is mounted onto the holding dock to hold the fastened member. The jutting plates are located longitudinally on the bottom in a protrusive manner. Each of the jutting plates has an outer surface on which a portion is extended outwards greater than other portion. The collet is encased in the sleeve. The sleeve has a tubular wall which has a plurality of segments corresponding to the jutting plates. Each segment has an inner surface on which a portion is extended inwards greater than other portion. When the greater extended inward portion of the tubular wall is in contact with the greater extended outwards portion of the jutting plate, the jutting plate is tilted inwards to press the fastened member.

摘要翻译： 一种紧固装置和保持架，其包括保持座，保持装置和紧固装置。 保持装置具有保持支架和紧固构件。 紧固装置包括夹头和套筒。 夹头具有底部和多个突出板。 将夹头安装到固定座上以固定紧固件。 突出板以突出的方式纵向位于底部。 每个突出板具有外表面，其中一部分向外延伸大于其它部分。 夹头套在袖子里。 套筒具有管状壁，其具有对应于突出板的多个段。 每个段具有内表面，其中一部分向内延伸大于其他部分。 当管状壁的较大延伸的向内部分与突出板的较大延伸的向外部分接触时，突出板向内倾斜以按压紧固构件。

公开(公告)号：US5932929A

公开(公告)日：1999-08-03

申请号：US944572

申请日：1997-10-06

申请人： Hon-Shung Lui ,  Ming-Chih Chung ,  Shun-Hsiang Chen

发明人： Hon-Shung Lui ,  Ming-Chih Chung ,  Shun-Hsiang Chen

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/02164 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/31625 ,  H01L21/76816 ,  H01L23/485 ,  H01L2924/0002

摘要： An improved method of forming a tunnel-free tungsten plug is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer of borophospho-tetraethoxysilane (BP-TEOS) is deposited overlying the semiconductor device structures. Contact openings are etched through the insulating layer to the underlying semiconductor device structures wherein a tunnel opens in the insulating layer between contact openings. The semiconductor substrate is covered with a first barrier metal layer. The semiconductor substrate is coated with a spin-on-glass layer wherein the contact openings and the tunnel are filled with the spin-on-glass. The spin-on-glass is anisotropically etched away whereby the spin-on-glass remains only within the tunnel. The semiconductor substrate is covered with a second barrier metal layer. The contact openings are filled with tungsten which is etched back to form tungsten plugs within the contact openings wherein the filled tunnel provides tunnel-free tungsten plugs in the fabrication of the integrated circuit device.

摘要翻译： 描述了形成无隧道钨塞的改进方法。 半导体器件结构设置在半导体衬底中和半导体衬底上。 沉积在半导体器件结构上的硼磷硅烷 - 四乙氧基硅烷（BP-TEOS）的绝缘层。 接触开口通过绝缘层蚀刻到下面的半导体器件结构，其中隧道在接触开口之间的绝缘层中开口。 半导体衬底被第一阻挡金属层覆盖。 半导体衬底涂覆有旋涂玻璃层，其中接触开口和隧道用旋涂玻璃填充。 旋涂玻璃被各向异性地蚀刻掉，因此旋涂玻璃仅保留在隧道内。 半导体衬底被第二阻挡金属层覆盖。 接触开口填充有钨，其被回蚀以在接触开口内形成钨塞，其中填充的隧道在集成电路器件的制造中提供无隧道的钨插塞。

公开(公告)号：US5895240A

公开(公告)日：1999-04-20

申请号：US884916

申请日：1997-06-30

申请人： Kuen-Joung Chuang ,  Ming-Chih Chung ,  Jyh-Feng Lin

发明人： Kuen-Joung Chuang ,  Ming-Chih Chung ,  Jyh-Feng Lin

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： The present invention provides a structure and a method of forming a stepped trench oxide structure for a semiconductor memory device. The stepped trench oxide structure has "oxide steps" (e.g., 252 or 34A, 34B, 34C) in the gate oxide 20 surrounding the tunnel oxide layer 30. The oxide steps 34 are formed where the oxide thinning effect normally thins the tunnel oxide 30 around the perimeter of the tunnel oxide layer 30. The oxide steps 34 252 compensate for the oxide thinning effect and eliminate the problems associated with the oxide thinning effects. The oxide steps are preferably formed using one photo mask to form two different sized openings using different photoresist exposure times. The preferred method comprises forming a first tunneling opening 220A in a first (gate) oxide layer 220. Then, forming a second oxide layer 250 over said exposed substrate and said first oxide layer 220. A second opening 250A (smaller than the first opening) is formed in the second oxide layer thereby forming a first step 252. Next, a third oxide layer 270 is formed over said exposed substrate, the first oxide layer 220 and the second oxide layer 250 thereby propagating the first step 252. The oxide thinning edge effect is eliminated by the first step.

摘要翻译： 本发明提供一种形成用于半导体存储器件的阶梯状沟槽氧化物结构的结构和方法。 阶梯状沟槽氧化物结构在围绕隧道氧化物层30的栅极氧化物20中具有“氧化物步骤”（例如，252或34A，34B，34C）。形成氧化物步骤34，其中氧化物稀化效应通常使隧道氧化物30沉降 围绕隧道氧化物层30的周边。氧化物步骤34 252补偿氧化物稀化效应并消除与氧化物稀化效应相关的问题。 氧化物步骤优选使用一个光掩模形成，以使用不同的光致抗蚀剂曝光时间形成两个不同尺寸的开口。 优选的方法包括在第一（栅极）氧化物层220中形成第一隧道开口220A。然后，在所述暴露的衬底和所述第一氧化物层220上形成第二氧化物层250.第二开口250A（小于第一开口） 形成在第二氧化物层中，从而形成第一步骤252.接下来，在所述暴露的基板上形成第三氧化物层270，第一氧化物层220和第二氧化物层250由此传播第一步骤252.氧化物变薄边缘 效果通过第一步消除。