Multiple exposure method for photo-exposing photosensitive layers upon
high step height topography substrate layers
    1.
    发明授权
    Multiple exposure method for photo-exposing photosensitive layers upon high step height topography substrate layers 失效
    在高阶高度地形基底层上曝光感光层的多重曝光方法

    公开(公告)号:US5631112A

    公开(公告)日:1997-05-20

    申请号:US726033

    申请日:1996-10-07

    IPC分类号: G03F7/20 G03F9/00

    CPC分类号: G03F7/70475 G03F7/2022

    摘要: A method for photo-exposing a blanket conformal photosensitive layer upon a high step height topography substrate layer. There is first provided a high step height topography substrate layer having a blanket conformal photosensitive layer formed thereupon. The high step height topography substrate layer has a first region having a first step height separated from a third region having a third step height by a second region having a second step height. The second step height is intermediate to the first step height and the third step height. The blanket conformal photosensitive layer is photo-exposed to form a first pattern upon the first region and the second region through use of a first reticle and a first photo-exposure condition. The first photo-exposure condition provides a first depth of focus suitable for at least the first region. In a separate process step, the blanket conformal photosensitive layer is photo-exposed to form a second pattern upon the second region and the third region through use of a second reticle and a second photo-exposure condition. The second photo-exposure condition provides a second depth of focus suitable for at least the third region. The first pattern upon the second region and the second pattern upon the second region overlap.

    摘要翻译: 一种用于在高阶高度地形衬底层上曝光毯状保形感光层的方法。 首先提供了具有在其上形成的覆盖层保形感光层的高阶高度地形基底层。 高台阶高度地形基底层具有第一区域,第一区域具有与具有第三台阶高度的第三区域分离的第一台阶高度与具有第二台阶高度的第二区域。 第二步高度处于第一步高度和第三步高度的中间。 通过使用第一掩模版和第一光曝光条件,在第一区域和第二区域上曝光毯状保形感光层以形成第一图案。 第一曝光条件提供适于至少第一区域的第一焦点深度。 在单独的工艺步骤中,通过使用第二掩模版和第二曝光条件,在第二区域和第三区域上曝光毯状保形光敏层以形成第二图案。 第二曝光条件提供适于至少第三区域的第二焦点深度。 第二区域上的第一图案和第二区域上的第二图案重叠。

    Methods of extracting fin heights and overlap capacitance and structures for performing the same
    2.
    发明授权
    Methods of extracting fin heights and overlap capacitance and structures for performing the same 有权
    提取翅片高度和重叠电容的方法和执行相同的结构

    公开(公告)号:US08629435B2

    公开(公告)日:2014-01-14

    申请号:US13411307

    申请日:2012-03-02

    IPC分类号: H01L23/58

    摘要: A first test structure includes a first isolation region, a first gate electrode over the first isolation region, a first and a second semiconductor fin, and a first contact plug over the first and the second semiconductor fins. A second test structure includes a second isolation region, a second gate electrode over the second isolation region, a third semiconductor fin and a dielectric fin, and a second contact plug over the third semiconductor fin. The first, the second, and the third semiconductor fins and the dielectric fin have substantially a same fin height. A method includes measuring a first capacitance between the first gate electrode and the first contact plug, measuring a second capacitance between the second gate electrode and the second contact plug, and calculating the same fin height from a capacitance difference between the second capacitance and the first capacitance.

    摘要翻译: 第一测试结构包括第一隔离区域,第一隔离区域上的第一栅极电极,第一和第二半导体鳍片以及第一和第二半导体鳍片上的第一接触插塞。 第二测试结构包括第二隔离区域,第二隔离区域上的第二栅极电极,第三半导体鳍片和介电鳍片,以及在第三半导体鳍片上的第二接触插塞。 第一,第二和第三半导体散热片和介电翅片具有大致相同的翅片高度。 一种方法包括测量第一栅电极和第一接触插塞之间的第一电容,测量第二栅电极和第二接触插塞之间的第二电容,并从第二电容和第一接触插塞之间的电容差计算相同的鳍高度 电容。

    Method of fabricating sidewall spacers for a self-aligned contact hole
    3.
    发明授权
    Method of fabricating sidewall spacers for a self-aligned contact hole 失效
    制造用于自对准接触孔的侧壁间隔件的方法

    公开(公告)号:US6033962A

    公开(公告)日:2000-03-07

    申请号:US121692

    申请日:1998-07-24

    CPC分类号: H01L21/76897

    摘要: A method for forming a self-aligned contact, (SAC), opening, for a semiconductor device, has been developed. The process features the formation of partial silicon nitride spacers, on the sides of polycide gate structures, via a partial anisotropic RIE procedure, applied to a silicon nitride layer, also resulting in a thin layer of silicon nitride remaining on regions between polycide gate structures. After deposition of an overlying insulator layer, a two step, anisotropic RIE procedure is used to create the SAC opening in the insulator layer, and in the underlying, thin silicon nitride layer. The first step, of the two step, SAC opening procedure, selectively removes first insulator layer, while the second step, of the two step, SAC opening procedure, selectively removes the thin silicon nitride layer.

    摘要翻译: 已经开发了用于形成用于半导体器件的自对准接触(SAC),开口的方法。 该方法的特征在于在多晶硅栅极结构的侧面上经由施加到氮化硅层的部分各向异性RIE程序形成部分氮化硅间隔物,同时也导致在多晶硅栅极结构之间的区域上留下薄层的氮化硅。 在沉积上覆绝缘体层之后,使用两步各向异性RIE程序来在绝缘体层中以及在下面的薄氮化硅层中形成SAC开口。 第一步,两步骤,SAC打开程序,选择性地去除第一绝缘体层,而第二步,两步,SAC打开程序,选择性地去除薄氮化硅层。

    Methods of Extracting Fin Heights and Overlap Capacitance and Structures for Performing the Same
    4.
    发明申请
    Methods of Extracting Fin Heights and Overlap Capacitance and Structures for Performing the Same 有权
    提取翅片高度和重叠电容及其结构的方法

    公开(公告)号:US20130228778A1

    公开(公告)日:2013-09-05

    申请号:US13411307

    申请日:2012-03-02

    IPC分类号: H01L29/78 H01L21/66

    摘要: A first test structure includes a first isolation region, a first gate electrode over the first isolation region, a first and a second semiconductor fin, and a first contact plug over the first and the second semiconductor fins. A second test structure includes a second isolation region, a second gate electrode over the second isolation region, a third semiconductor fin and a dielectric fin, and a second contact plug over the third semiconductor fin. The first, the second, and the third semiconductor fins and the dielectric fin have substantially a same fin height. A method includes measuring a first capacitance between the first gate electrode and the first contact plug, measuring a second capacitance between the second gate electrode and the second contact plug, and calculating the same fin height from a capacitance difference between the second capacitance and the first capacitance.

    摘要翻译: 第一测试结构包括第一隔离区域,第一隔离区域上的第一栅极电极,第一和第二半导体鳍片以及第一和第二半导体鳍片上的第一接触插塞。 第二测试结构包括第二隔离区域,第二隔离区域上的第二栅极电极,第三半导体鳍片和介电鳍片,以及在第三半导体鳍片上的第二接触插塞。 第一,第二和第三半导体散热片和介电翅片具有大致相同的翅片高度。 一种方法包括测量第一栅电极和第一接触插塞之间的第一电容,测量第二栅电极和第二接触插塞之间的第二电容,并从第二电容和第一接触插塞之间的电容差计算相同的鳍高度 电容。