公开(公告)号：US6033962A

公开(公告)日：2000-03-07

申请号：US121692

申请日：1998-07-24

申请人： Erik S. Jeng ,  Hung-Yi Luo ,  Yue-Feng Chen ,  Ming-Horn Tsai

发明人： Erik S. Jeng ,  Hung-Yi Luo ,  Yue-Feng Chen ,  Ming-Horn Tsai

IPC分类号： H01L21/60 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/76897

摘要： A method for forming a self-aligned contact, (SAC), opening, for a semiconductor device, has been developed. The process features the formation of partial silicon nitride spacers, on the sides of polycide gate structures, via a partial anisotropic RIE procedure, applied to a silicon nitride layer, also resulting in a thin layer of silicon nitride remaining on regions between polycide gate structures. After deposition of an overlying insulator layer, a two step, anisotropic RIE procedure is used to create the SAC opening in the insulator layer, and in the underlying, thin silicon nitride layer. The first step, of the two step, SAC opening procedure, selectively removes first insulator layer, while the second step, of the two step, SAC opening procedure, selectively removes the thin silicon nitride layer.

摘要翻译： 已经开发了用于形成用于半导体器件的自对准接触（SAC），开口的方法。 该方法的特征在于在多晶硅栅极结构的侧面上经由施加到氮化硅层的部分各向异性RIE程序形成部分氮化硅间隔物，同时也导致在多晶硅栅极结构之间的区域上留下薄层的氮化硅。 在沉积上覆绝缘体层之后，使用两步各向异性RIE程序来在绝缘体层中以及在下面的薄氮化硅层中形成SAC开口。 第一步，两步骤，SAC打开程序，选择性地去除第一绝缘体层，而第二步，两步，SAC打开程序，选择性地去除薄氮化硅层。

公开(公告)号：US6150213A

公开(公告)日：2000-11-21

申请号：US111685

申请日：1998-07-08

申请人： Hung-Yi Luo ,  Erik S. Jeng ,  Yue-Feng Chen

发明人： Hung-Yi Luo ,  Erik S. Jeng ,  Yue-Feng Chen

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/91 ,  H01L27/10873

摘要： The present invention includes forming polysilicon plugs between the gate structures and word lines in a BPSG layer formed on the gate structures and the word lines. A polysilicon layer, a tungsten silicide layer and a silicon oxide layer are sequentially formed on the BPSG layer. Then, the multi-layers are etched to the surface of the BPSG layer. Next, the BPSG layer is slightly etched to expose the polysilicon plug. Oxide spacers are formed on the sidewalls of the layers. A silicon nitride layer is formed over the bit lines, oxide spacers and on the polysilicon plugs. An oxide layer is formed on the silicon nitride layer. Subsequently, the oxide layer is patterned to form node contact holes. An etching is used to etch the silicon nitride layer. A first conductive layer is formed along the surface of the oxide layer, the contact holes. The top portion of the first conductive layer is removed. The oxide layer is removed to expose the silicon nitride layer. A dielectric film is deposited along the surface of the first conductive layer. Finally, a second conductive layer is formed over the dielectric film.

摘要翻译： 本发明包括在形成在栅极结构和字线上的BPSG层中的栅极结构和字线之间形成多晶硅插塞。 在BPSG层上依次形成多晶硅层，硅化钨层和氧化硅层。 然后，将多层蚀刻到BPSG层的表面。 接下来，稍微蚀刻BPSG层以暴露多晶硅插塞。 在层的侧壁上形成氧化物间隔物。 在位线，氧化物间隔物和多晶硅插塞上形成氮化硅层。 在氮化硅层上形成氧化物层。 随后，对氧化层进行图案化以形成节点接触孔。 蚀刻用于蚀刻氮化硅层。 沿着氧化物层的表面，接触孔形成第一导电层。 去除第一导电层的顶部。 去除氧化物层以露出氮化硅层。 沿着第一导电层的表面沉积电介质膜。 最后，在电介质膜上形成第二导电层。

公开(公告)号：US6100137A

公开(公告)日：2000-08-08

申请号：US373247

申请日：1999-08-12

申请人： Yue-Feng Chen ,  Liang-Gi Yao ,  Guei-Chi Guo ,  Hung-Yi Luo

发明人： Yue-Feng Chen ,  Liang-Gi Yao ,  Guei-Chi Guo ,  Hung-Yi Luo

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L28/91 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10888

摘要： A process for creating a crown shaped storage node structure, for a DRAM capacitor structure, featuring the use of a silicon oxynitride layer, underlying the crown shaped storage node structure, has been developed. A silicon oxynitride layer is placed overlying the interlevel dielectric layers that used to protect underlying DRAM elements, and placed underlying a capacitor opening in an overlying insulator layer. A selective RIE procedure is used to create the capacitor opening, in an insulator layer, with the RIE procedure terminating at the exposure of the underlying silicon oxynitride layer. After creation of the crown shaped storage node structure, in the capacitor opening, overlying the silicon oxynitride layer at the bottom of the capacitor opening, the insulator layer used for formation of the capacitor opening, is selectively removed from the regions of silicon oxynitride layer, not covered by the overlying crown shaped storage node structure, using wet etch procedures.

摘要翻译： 已经开发了一种用于创建用于DRAM电容器结构的冠形存储节点结构的方法，其特征在于使用位于冠形存储节点结构下方的氮氧化硅层。 将氮氧化硅层放置在用于保护下层DRAM元件的层间电介质层的上方，并置于上层绝缘体层中的电容器开口下方。 使用选择性RIE程序在绝缘体层中产生电容器开口，其中RIE程序在下一个氮氧化硅层的曝光下终止。 在形成冠形存储节点结构之后，在电容器开口中，覆盖电容器开口底部的氧氮化硅层，用于形成电容器开口的绝缘体层从氮氧化硅层的区域选择性地去除， 不覆盖上覆冠状储层结构，采用湿蚀刻程序。

公开(公告)号：US5904521A

公开(公告)日：1999-05-18

申请号：US919393

申请日：1997-08-28

申请人： Erik S. Jeng ,  Yue-Feng Chen

发明人： Erik S. Jeng ,  Yue-Feng Chen

IPC分类号： H01L21/8242

CPC分类号： H01L27/10852

摘要： A method for forming a contact hole of a capacitor of a DRAM cell is disclosed. The method includes forming a first conductive layer on a semiconductor substrate, and forming a first dielectric layer on the first conductive layer. After patterning to etch the first dielectric layer and the first conductive layer, a second dielectric layer is formed on the semiconductor substrate and the first dielectric layer. Next, the second dielectric layer is anisotropically etched back to form a first spacer on sidewalls of the first dielectric layer and the first conductive layer. A first silicon oxide layer is formed over the semiconductor substrate, the first dielectric layer, the first spacer, followed by patterning to etch the first silicon oxide layer, wherein the first spacer and the first dielectric layer are used for facilitating self-aligned etching. Thereafter, a second conductive layer is formed over the semiconductor substrate, wherein surface of the first silicon oxide layer is exposed, and a second silicon oxide layer is formed over the second conductive layer and the first silicon oxide layer. Finally, patterning to etch a portion of the second silicon oxide layer to expose a portion of the second conductive layer, therefore a contact hole of the capacitor is formed.

摘要翻译： 公开了一种用于形成DRAM单元的电容器的接触孔的方法。 该方法包括在半导体衬底上形成第一导电层，并在第一导电层上形成第一介电层。 在图案化以蚀刻第一介电层和第一导电层之后，在半导体衬底和第一介电层上形成第二电介质层。 接下来，第二介电层被各向异性地回蚀以在第一介电层和第一导电层的侧壁上形成第一间隔物。 在半导体衬底上形成第一氧化硅层，第一介电层，第一间隔物，然后构图以蚀刻第一氧化硅层，其中第一间隔物和第一介电层用于促进自对准蚀刻。 此后，在半导体衬底上形成第二导电层，其中露出第一氧化硅层的表面，并在第二导电层和第一氧化硅层上形成第二氧化硅层。 最后，图案化以蚀刻第二氧化硅层的一部分以暴露第二导电层的一部分，因此形成电容器的接触孔。

公开(公告)号：US6037211A

公开(公告)日：2000-03-14

申请号：US841836

申请日：1997-05-05

申请人： Erik S. Jeng ,  Yue-Feng Chen ,  Bi-Ling Chen

发明人： Erik S. Jeng ,  Yue-Feng Chen ,  Bi-Ling Chen

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L27/10844 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897

摘要： A method of fabricating contact holes in high density integrated circuits uses landing plugs to reduce the aspect ratio of the the node contact holes in order to improve the processing window of deep contact holes. Along with nitride spacers on the sidewalls of a transistor gate structure, polysilicon hard masks and polysilicon spacers are used as etching masks in a self-aligned contact process. In addition, the landing plugs incorporate the polysilicon spacers as part of landing plug to increase the contact area. As a result, wide contact processing windows can be achieved in high density integrated circuits.

摘要翻译： 在高密度集成电路中制造接触孔的方法使用着陆塞以减小节点接触孔的纵横比，以改善深接触孔的加工窗口。 随着在晶体管栅极结构的侧壁上的氮化物间隔物，多晶硅硬掩模和多晶硅间隔物用作自对准接触工艺中的蚀刻掩模。 此外，着陆塞将多晶硅间隔件作为着陆塞的一部分，以增加接触面积。 因此，可以在高密度集成电路中实现广泛的接触处理窗口。

公开(公告)号：US20050133940A1

公开(公告)日：2005-06-23

申请号：US10865746

申请日：2004-06-14

申请人： Mou-Jung Chen ,  Chien-Hsien Song ,  Yui-Su Lee ,  Chien-Yuan Lee ,  Yue-Feng Chen

发明人： Mou-Jung Chen ,  Chien-Hsien Song ,  Yui-Su Lee ,  Chien-Yuan Lee ,  Yue-Feng Chen

IPC分类号： H01L23/544 ,  H01L21/76 ,  H01L21/4763

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for protecting alignment marks. A substrate comprising a plurality of alignment marks is provided, wherein the alignment mark comprises a plurality of trenches. A plurality of protective patterns are formed on the substrate by depositing a protective layer and patterning the same to protect the alignment marks from damage during subsequent CMP process.

摘要翻译： 用于保护对准标记的方法和结构。 提供了包括多个对准标记的衬底，其中对准标记包括多个沟槽。 通过沉积保护层并对其进行图案化而在基板上形成多个保护图案，以保护对准标记免于后续CMP工艺中的损坏。

公开(公告)号：US06143664A

公开(公告)日：2000-11-07

申请号：US928205

申请日：1997-09-12

申请人： Liang-Gi Yao ,  Chung-Ju Lee ,  Yue-Feng Chen ,  Wei-Ray Lin ,  Yeur-Luen Tu

发明人： Liang-Gi Yao ,  Chung-Ju Lee ,  Yue-Feng Chen ,  Wei-Ray Lin ,  Yeur-Luen Tu

IPC分类号： H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76819

摘要： A method of planarizing a structure having an interpoly layer is disclosed. The method includes forming an undoped silica glass layer on at least a polysilicon region formed on a semiconductor substrate. Next, a spin-on-glass layer is formed over the undoped silica glass layer. Finally, the spin-on-glass layer is etched back, thereby planarizing the structure having the interpoly layer.

摘要翻译： 公开了一种平面化具有多晶硅层的结构的方法。 该方法包括在至少形成在半导体衬底上的多晶硅区域上形成未掺杂的二氧化硅玻璃层。 接下来，在未掺杂的二氧化硅玻璃层上形成旋涂玻璃层。 最后，将旋涂玻璃层回蚀刻，从而使具有多晶硅层的结构平坦化。

公开(公告)号：US07129134B2

公开(公告)日：2006-10-31

申请号：US10992729

申请日：2004-11-22

申请人： Jui-Hsiang Yang ,  Ing-Ruey Liaw ,  Yue-Feng Chen

发明人： Jui-Hsiang Yang ,  Ing-Ruey Liaw ,  Yue-Feng Chen

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A fabrication method for flash memory. The method comprises providing a substrate, and a first insulation layer, a first conductive layer, a second insulation layer thereon. The second insulation layer is patterned to form a first opening and reveal a part of the first conductive layer, and a third insulation layer is formed on the first opening sidewall to form a second opening. The first conductive layer and the first insulation layer beneath the second opening are etched to expose the substrate surface, and a spacer is formed on the second opening sidewall. A source region is formed in the exposed substrate and a source line with a concave surface is formed in the second opening. A mask layer is formed on the source line concave surface.

摘要翻译： 一种闪存的制造方法。 该方法包括在其上提供衬底和第一绝缘层，第一导电层，第二绝缘层。 图案化第二绝缘层以形成第一开口并露出第一导电层的一部分，并且第三绝缘层形成在第一开口侧壁上以形成第二开口。 蚀刻第二开口下面的第一导电层和第一绝缘层以露出衬底表面，并且在第二开口侧壁上形成间隔物。 源区域形成在暴露的衬底中，并且在第二开口中形成具有凹面的源极线。 在源极线凹面上形成掩模层。

公开(公告)号：US20050181563A1

公开(公告)日：2005-08-18

申请号：US10992729

申请日：2004-11-22

申请人： Jui-Hsiang Yang ,  Ing-Ruey Liaw ,  Yue-Feng Chen

发明人： Jui-Hsiang Yang ,  Ing-Ruey Liaw ,  Yue-Feng Chen

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A fabrication method for flash memory. The method comprises providing a substrate, and a first insulation layer, a first conductive layer, a second insulation layer thereon. The second insulation layer is patterned to form a first opening and reveal a part of the first conductive layer, and a third insulation layer is formed on the first opening sidewall to form a second opening. The first conductive layer and the first insulation layer beneath the second opening are etched to expose the substrate surface, and a spacer is formed on the second opening sidewall. A source region is formed in the exposed substrate and a source line with a concave surface is formed in the second opening. A mask layer is formed on the source line concave surface.

摘要翻译： 一种闪存的制造方法。 该方法包括在其上提供衬底和第一绝缘层，第一导电层，第二绝缘层。 图案化第二绝缘层以形成第一开口并露出第一导电层的一部分，并且第三绝缘层形成在第一开口侧壁上以形成第二开口。 蚀刻第二开口下面的第一导电层和第一绝缘层以露出衬底表面，并且在第二开口侧壁上形成间隔物。 源区域形成在暴露的衬底中，并且在第二开口中形成具有凹面的源极线。 在源极线凹面上形成掩模层。

公开(公告)号：US06294474B1

公开(公告)日：2001-09-25

申请号：US09425906

申请日：1999-10-25

申请人： Wen-Tsing Tzeng ,  Yue-Feng Chen ,  Kau-Jan Wang

发明人： Wen-Tsing Tzeng ,  Yue-Feng Chen ,  Kau-Jan Wang

IPC分类号： H01L21302

CPC分类号： H01L27/10894 ,  H01L23/5258 ,  H01L27/10852 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is described for progressively forming a fuse access opening for laser trimming in an integrated circuit with improved control of dielectric thickness over the fuse. A dielectric layer is formed over the fuse and a polysilicon layer is then patterned over the fuse to form a first etch stop. An ILD layer is added and a second etch stop is formed in a first metal layer on the ILD layer over the first etch stop. The second etch stop serves to protect the ILD layer over the fuse from being etched by an ARC over etch during the via etching in a first IMD layer. A first portion of the laser access window is formed during the via etching of the first IMD layer. The second etch stop is then removed by the second metal patterning etch, exposing the ILD layer over the first etch stop at it's original thickness. A passivation layer is deposited and patterned to form access openings to bonding pads as well as to further open the laser access window to the first etch stop. The first etch stop prevents penetration of the subjacent insulative layer over the fuse, thereby maintaining a controlled uniform thickness of that layer. When the bonding pads are opened, including the removal of an ARC on their surface, the etchant conditions are changed to remove the etch stop and subsequently a portion of the subjacent insulative layer over the fuse leaving a precise and uniform thickness of dielectric material over the fuse. The process fits conveniently within the framework of an existing process and does not introduce any additional steps.

摘要翻译： 描述了用于逐渐形成用于集成电路中的激光修整的熔丝进入开口的方法，其中改进了熔丝上的电介质厚度的控制。 在熔丝上方形成电介质层，然后在保险丝上形成多晶硅层以形成第一蚀刻停止。 添加ILD层，并且在第一蚀刻停止点上的ILD层上的第一金属层中形成第二蚀刻停止。 第二蚀刻停止器用于保护熔丝上的ILD层在第一IMD层中的通孔蚀刻期间被ARC过蚀刻蚀刻。 在第一IMD层的通孔蚀刻期间形成激光入口窗口的第一部分。 然后通过第二金属图案化蚀刻去除第二蚀刻停止层，在其初始厚度下将ILD层暴露在第一蚀刻停止点上。 钝化层被沉积并图案化以形成接合焊盘的访问开口，以及进一步将激光入口窗口打开到第一蚀刻停止。 第一蚀刻停止件防止相邻绝缘层穿过保险丝，从而保持该层的受控的均匀厚度。 当接合焊盘打开时，包括在其表面上去除ARC，蚀刻剂条件被改变以去除蚀刻停止层，随后在熔丝上方的一部分相邻的绝缘层留下精确而均匀的介电材料厚度 保险丝。 该过程在现有过程的框架内方便地配置，并且不引入任何附加步骤。