公开(公告)号：US6033962A

公开(公告)日：2000-03-07

申请号：US121692

申请日：1998-07-24

申请人： Erik S. Jeng ,  Hung-Yi Luo ,  Yue-Feng Chen ,  Ming-Horn Tsai

发明人： Erik S. Jeng ,  Hung-Yi Luo ,  Yue-Feng Chen ,  Ming-Horn Tsai

IPC分类号： H01L21/60 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/76897

摘要： A method for forming a self-aligned contact, (SAC), opening, for a semiconductor device, has been developed. The process features the formation of partial silicon nitride spacers, on the sides of polycide gate structures, via a partial anisotropic RIE procedure, applied to a silicon nitride layer, also resulting in a thin layer of silicon nitride remaining on regions between polycide gate structures. After deposition of an overlying insulator layer, a two step, anisotropic RIE procedure is used to create the SAC opening in the insulator layer, and in the underlying, thin silicon nitride layer. The first step, of the two step, SAC opening procedure, selectively removes first insulator layer, while the second step, of the two step, SAC opening procedure, selectively removes the thin silicon nitride layer.

摘要翻译： 已经开发了用于形成用于半导体器件的自对准接触（SAC），开口的方法。 该方法的特征在于在多晶硅栅极结构的侧面上经由施加到氮化硅层的部分各向异性RIE程序形成部分氮化硅间隔物，同时也导致在多晶硅栅极结构之间的区域上留下薄层的氮化硅。 在沉积上覆绝缘体层之后，使用两步各向异性RIE程序来在绝缘体层中以及在下面的薄氮化硅层中形成SAC开口。 第一步，两步骤，SAC打开程序，选择性地去除第一绝缘体层，而第二步，两步，SAC打开程序，选择性地去除薄氮化硅层。

公开(公告)号：US6150213A

公开(公告)日：2000-11-21

申请号：US111685

申请日：1998-07-08

申请人： Hung-Yi Luo ,  Erik S. Jeng ,  Yue-Feng Chen

发明人： Hung-Yi Luo ,  Erik S. Jeng ,  Yue-Feng Chen

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/91 ,  H01L27/10873

摘要： The present invention includes forming polysilicon plugs between the gate structures and word lines in a BPSG layer formed on the gate structures and the word lines. A polysilicon layer, a tungsten silicide layer and a silicon oxide layer are sequentially formed on the BPSG layer. Then, the multi-layers are etched to the surface of the BPSG layer. Next, the BPSG layer is slightly etched to expose the polysilicon plug. Oxide spacers are formed on the sidewalls of the layers. A silicon nitride layer is formed over the bit lines, oxide spacers and on the polysilicon plugs. An oxide layer is formed on the silicon nitride layer. Subsequently, the oxide layer is patterned to form node contact holes. An etching is used to etch the silicon nitride layer. A first conductive layer is formed along the surface of the oxide layer, the contact holes. The top portion of the first conductive layer is removed. The oxide layer is removed to expose the silicon nitride layer. A dielectric film is deposited along the surface of the first conductive layer. Finally, a second conductive layer is formed over the dielectric film.

摘要翻译： 本发明包括在形成在栅极结构和字线上的BPSG层中的栅极结构和字线之间形成多晶硅插塞。 在BPSG层上依次形成多晶硅层，硅化钨层和氧化硅层。 然后，将多层蚀刻到BPSG层的表面。 接下来，稍微蚀刻BPSG层以暴露多晶硅插塞。 在层的侧壁上形成氧化物间隔物。 在位线，氧化物间隔物和多晶硅插塞上形成氮化硅层。 在氮化硅层上形成氧化物层。 随后，对氧化层进行图案化以形成节点接触孔。 蚀刻用于蚀刻氮化硅层。 沿着氧化物层的表面，接触孔形成第一导电层。 去除第一导电层的顶部。 去除氧化物层以露出氮化硅层。 沿着第一导电层的表面沉积电介质膜。 最后，在电介质膜上形成第二导电层。

公开(公告)号：US06265296B1

公开(公告)日：2001-07-24

申请号：US09436688

申请日：1999-11-08

申请人： Tzu-Shih Yen ,  Erik S. Jeng ,  Hao-Chieh Liu ,  Hung-Yi Luo

发明人： Tzu-Shih Yen ,  Erik S. Jeng ,  Hao-Chieh Liu ,  Hung-Yi Luo

IPC分类号： H01L213205

CPC分类号： H01L21/76897 ,  H01L21/31144

摘要： A method for making self-aligned contacts on a semiconductor substrate using a hard mask. After the transistor is formed, a blanket insulating layer is formed on said semiconductor substrate. A hard mask having openings on the blanket insulating layer is formed over the insulating layer. The openings overlay the source/drain region and part of the gate electrode structure. Using the patterned hard mask, the insulating layer is etched to the gate electrode protecting layer. Then self-aligned contacts is completed by etching the insulating layer to expose the source/drain regions using the gate electrode protecting layer and the insulating sidewall spacers as the mask.

摘要翻译： 一种使用硬掩模在半导体衬底上进行自对准接触的方法。 在形成晶体管之后，在所述半导体衬底上形成覆盖绝缘层。 在绝缘层上形成有在绝缘层上具有开口的硬掩模。 开口覆盖源极/漏极区域和栅电极结构的一部分。 使用图案化的硬掩模，将绝缘层蚀刻到栅电极保护层。 然后通过蚀刻绝缘层来完成自对准触点，以使用栅电极保护层和绝缘侧壁间隔件作为掩模来暴露源/漏区。

公开(公告)号：US06124192A

公开(公告)日：2000-09-26

申请号：US405062

申请日：1999-09-27

申请人： Erik S. Jeng ,  Tzu-Shih Yen ,  Hung-Yi Luo

发明人： Erik S. Jeng ,  Tzu-Shih Yen ,  Hung-Yi Luo

IPC分类号： H01L21/60 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L21/76897 ,  H01L23/5226 ,  H01L2924/0002

摘要： A process for fabricating an interconnect structure, featuring contact of the interconnect structure, to an exposed side of an underlying conductive plug structure, where the conductive plug structure is used to communicate with an active device region in a semiconductor substrate, has been developed. The process features the use of simple photolithographic patterns, such as a stripe opening, exposing a group of gate structures, and a group of spaces, located between the gate structures, to be used for subsequent contact plug formation. This is in contrast to conventional processing, in which a more difficult photolithographic procedure is used to create smaller, individual openings, to individual spaces between gate structures. In addition this invention features a self-aligned opening, exposing only a side of a contact plug structure. An overlying interconnect structure then contacts only the exposed side of the underlying contact plug structure, again reducing photolithographic difficulties, encountered with conventional methods of creating a non-self aligned opening to an underlying contact plug.

摘要翻译： 已经开发了用于制造互连结构的方法，该互连结构具有互连结构的接触到底层导电插塞结构的暴露侧，其中导电插塞结构用于与半导体衬底中的有源器件区域连通。 该方法特征在于使用简单的光刻图案，例如条形开口，暴露一组栅极结构，以及位于栅极结构之间的一组空间，用于随后的接触插塞形成。 这与常规处理相反，其中使用更困难的光刻工艺来为门结构之间的各个空间创建更小的单个开口。 此外，本发明具有自对准开口，仅暴露接触插塞结构的一侧。 上覆的互连结构然后仅接触下面的接触插塞结构的暴露侧，再次降低光刻困难，这与传统的向下面的接触插塞产生非自对准开口的方法相碰。

公开(公告)号：US5904521A

公开(公告)日：1999-05-18

申请号：US919393

申请日：1997-08-28

申请人： Erik S. Jeng ,  Yue-Feng Chen

发明人： Erik S. Jeng ,  Yue-Feng Chen

IPC分类号： H01L21/8242

CPC分类号： H01L27/10852

摘要： A method for forming a contact hole of a capacitor of a DRAM cell is disclosed. The method includes forming a first conductive layer on a semiconductor substrate, and forming a first dielectric layer on the first conductive layer. After patterning to etch the first dielectric layer and the first conductive layer, a second dielectric layer is formed on the semiconductor substrate and the first dielectric layer. Next, the second dielectric layer is anisotropically etched back to form a first spacer on sidewalls of the first dielectric layer and the first conductive layer. A first silicon oxide layer is formed over the semiconductor substrate, the first dielectric layer, the first spacer, followed by patterning to etch the first silicon oxide layer, wherein the first spacer and the first dielectric layer are used for facilitating self-aligned etching. Thereafter, a second conductive layer is formed over the semiconductor substrate, wherein surface of the first silicon oxide layer is exposed, and a second silicon oxide layer is formed over the second conductive layer and the first silicon oxide layer. Finally, patterning to etch a portion of the second silicon oxide layer to expose a portion of the second conductive layer, therefore a contact hole of the capacitor is formed.

摘要翻译： 公开了一种用于形成DRAM单元的电容器的接触孔的方法。 该方法包括在半导体衬底上形成第一导电层，并在第一导电层上形成第一介电层。 在图案化以蚀刻第一介电层和第一导电层之后，在半导体衬底和第一介电层上形成第二电介质层。 接下来，第二介电层被各向异性地回蚀以在第一介电层和第一导电层的侧壁上形成第一间隔物。 在半导体衬底上形成第一氧化硅层，第一介电层，第一间隔物，然后构图以蚀刻第一氧化硅层，其中第一间隔物和第一介电层用于促进自对准蚀刻。 此后，在半导体衬底上形成第二导电层，其中露出第一氧化硅层的表面，并在第二导电层和第一氧化硅层上形成第二氧化硅层。 最后，图案化以蚀刻第二氧化硅层的一部分以暴露第二导电层的一部分，因此形成电容器的接触孔。

公开(公告)号：US5895239A

公开(公告)日：1999-04-20

申请号：US152313

申请日：1998-09-14

申请人： Erik S. Jeng ,  Hung-Yi Luo

发明人： Erik S. Jeng ,  Hung-Yi Luo

IPC分类号： H01L21/8242

CPC分类号： H01L27/10844 ,  H01L27/10852 ,  H01L27/10873

摘要： DRAM cells having self-aligned node-contacts-to-bit lines with tungsten landing plug contacts for reduced aspect ratio contact openings and via holes is achieved. A planar insulating layer is formed, and openings for bit line contacts, node contacts, and landing plugs on the chip periphery are concurrently etched. A W/TiN layer is patterned to form bit lines, capacitor node, and multilevel contact landing plugs on the DRAM chip. The landing plugs reduce the aspect ratio of the openings for the multilevel contacts. Bit line sidewall spacers are formed, and a BPSG is deposited and planarized. Capacitor openings are etched in the BPSG aligned over the node contacts. A conformal conducting layer is deposited, and a polymer is deposited and planarized. The polymer and the conducting layer are polished back to complete the capacitor bottom electrodes in the capacitor openings. The polymer is removed. An inter-electrode dielectric layer and a conformal conducting layer (top electrode) are deposited and patterned to complete the capacitors. Capacitor openings are filled with a planarized insulator and the interlevel contact openings etched to the landing plugs therein have reduced aspect ratios. W/TiN plugs are formed in the openings, and a metal layer (Ti--TiN/AlCu/TiN) is deposited and patterned to form the first level of metal interconnections.

摘要翻译： 实现具有用于减小纵横比接触开口和通孔的具有钨接头插头触头的具有自对准节点接触对位线的DRAM单元。 形成平面绝缘层，同时蚀刻芯片周边上的位线接触，节点接触和着陆塞的开口。 图案化W / TiN层以在DRAM芯片上形成位线，电容器节点和多电平接触着陆插头。 着陆塞降低了多层接触孔的纵横比。 形成位线侧壁间隔物，并沉积并平坦化BPSG。 电容器开口在BPSG上蚀刻，在节点触点上对齐。 沉积保形导电层，并沉积和平坦化聚合物。 聚合物和导电层被抛光以完成电容器开口中的电容器底部电极。 去除聚合物。 电极间电介质层和保形导电层（顶电极）被沉积并图案化以完成电容器。 电容器开口填充有平坦化的绝缘体，并且蚀刻到其中的层压塞的层间接触开口具有减小的纵横比。 在开口中形成W / TiN插塞，并且沉积并图案化金属层（Ti-TiN / AlCu / TiN）以形成第一级金属互连。

公开(公告)号：US6037211A

公开(公告)日：2000-03-14

申请号：US841836

申请日：1997-05-05

申请人： Erik S. Jeng ,  Yue-Feng Chen ,  Bi-Ling Chen

发明人： Erik S. Jeng ,  Yue-Feng Chen ,  Bi-Ling Chen

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L27/10844 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897

摘要： A method of fabricating contact holes in high density integrated circuits uses landing plugs to reduce the aspect ratio of the the node contact holes in order to improve the processing window of deep contact holes. Along with nitride spacers on the sidewalls of a transistor gate structure, polysilicon hard masks and polysilicon spacers are used as etching masks in a self-aligned contact process. In addition, the landing plugs incorporate the polysilicon spacers as part of landing plug to increase the contact area. As a result, wide contact processing windows can be achieved in high density integrated circuits.

摘要翻译： 在高密度集成电路中制造接触孔的方法使用着陆塞以减小节点接触孔的纵横比，以改善深接触孔的加工窗口。 随着在晶体管栅极结构的侧壁上的氮化物间隔物，多晶硅硬掩模和多晶硅间隔物用作自对准接触工艺中的蚀刻掩模。 此外，着陆塞将多晶硅间隔件作为着陆塞的一部分，以增加接触面积。 因此，可以在高密度集成电路中实现广泛的接触处理窗口。

公开(公告)号：US07457154B2

公开(公告)日：2008-11-25

申请号：US11445205

申请日：2006-06-02

申请人： Tzu-shih Yen ,  Erik S. Jeng

发明人： Tzu-shih Yen ,  Erik S. Jeng

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C11/5692 ,  G11C17/12 ,  H01L27/112 ,  H01L27/115 ,  H01L29/4234 ,  H01L29/7923

摘要： A memory system comprising a memory array having a plurality of memory units, a column decoder, a row decoder, a selecting/driving circuit and a sensing circuit is disclosed. Each memory unit comprises a gate electrode coupled to a word lines, a source region coupled to a source line or a first bit line, a drain region coupled to a drain line or a second bit line, a first spacer between the source region and the gate electrode and a second spacer between the drain region and the gate electrode. When a first-bit program operation is performed on the memory unit, a switch-on signal is applied to the gate, a programming signal is applied to the source region and the drain region is switched to ground. As the memory unit is activated, the carriers are injected and stored in a first spacer, thus represents a first bit in the memory unit.

摘要翻译： 一种存储器系统，包括具有多个存储器单元的存储器阵列，列解码器，行解码器，选择/驱动电路和感测电路。 每个存储器单元包括耦合到字线的栅电极，耦合到源极线或第一位线的源极区域，耦合到漏极线或第二位线的漏极区域，源区域和第二位线之间的第一间隔物 栅极电极和漏极区域和栅电极之间的第二间隔物。 当对存储器单元执行第一位编程操作时，将接通信号施加到栅极，将编程信号施加到源极区域，并将漏极区域切换到地。 当存储器单元被激活时，载体被注入并存储在第一间隔件中，因此代表存储器单元中的第一位。

公开(公告)号：US07179708B2

公开(公告)日：2007-02-20

申请号：US10891373

申请日：2004-07-14

申请人： Erik S. Jeng ,  Wu-Ching Chou ,  Li-Kang Wu ,  Chien-Chen Li

发明人： Erik S. Jeng ,  Wu-Ching Chou ,  Li-Kang Wu ,  Chien-Chen Li

IPC分类号： H01L21/336

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L29/4234

摘要： A process for fabricating non-volatile memory by tilt-angle ion implantation comprises essentially the steps of implanting sideling within a nitride dielectric layer heterogeneous elements such as, for example, Ge, Si, N2, O2, and the like, for forming traps capable of capturing more electrons within the nitride dielectric layer such that electrons can be prevented from binding together as the operation time increased; etching off both ends of the original upper and underlying oxide layers to reduce the structural destruction caused by the implantation of heterogeneous elements; and finally, depositing an oxide gate interstitial wall to eradicate electron loss and hence promote the reliability of the device.

摘要翻译： 通过倾斜角度离子注入制造非易失性存储器的方法基本上包括以下步骤：在氮化物电介质层中注入异质元素，例如Ge，Si，N 2，O 2等，以形成能够捕获的阱 在氮化物电介质层内捕获更多的电子，使得当操作时间增加时可以防止电子结合在一起; 蚀刻原始上部和下部氧化物层的两端以减少由异质元素的注入引起的结构破坏; 最后，沉积氧化物栅间隙壁以消除电子损失，从而提高器件的可靠性。

公开(公告)号：US07072210B2

公开(公告)日：2006-07-04

申请号：US10831199

申请日：2004-04-26

申请人： Erik S. Jeng

发明人： Erik S. Jeng

IPC分类号： G11C16/04

CPC分类号： H01L27/11206 ,  G11C16/0475 ,  G11C17/12 ,  H01L21/28282 ,  H01L27/112 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： A memory array including a plurality of word lines, a plurality of first source/drain lines, a plurality of second source/drain lines, and a plurality of memory units. Each memory unit includes a gate electrode coupled to one of the word lines, a first source/drain region coupled to one of the first source/drain lines or first bit lines, a second source/drain region coupled to one of the second source/drain lines or second bit lines, a first spacer between the first source/drain region and the gate electrode to store electrons or electric charges, and a second spacer between the second source/drain region and the gate electrode to store electrons or electric charges.

摘要翻译： 包括多个字线，多个第一源极/漏极线，多个第二源极/漏极线以及多个存储器单元的存储器阵列。 每个存储器单元包括耦合到字线之一的栅电极，耦合到第一源极/漏极线或第一位线之一的第一源极/漏极区域，耦合到第二源极/漏极区域中的一个的第二源极/漏极区域， 漏极线或第二位线，在第一源极/漏极区域和栅极电极之间存储电子或电荷的第一间隔物，以及在第二源极/漏极区域和栅极电极之间的第二间隔物，以存储电子或电荷。