公开(公告)号：US07443890B2

公开(公告)日：2008-10-28

申请号：US10602227

申请日：2003-06-24

Applicant: Mohammad Nejad ,  Ali Ghiasi

Inventor： Mohammad Nejad ,  Ali Ghiasi

IPC: H04J3/02

CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: A multi-stage bit stream multiplexer that divides multiplexing functions between two or more integrated circuits. The first integrated circuit receives 16 bit streams to produce 4 output bits streams with a nominal data rate of 10 GBPS. A second integrated circuit multiplexes the 4 streams and to a bit stream with a data rate of 40 GBPS. The first IC is made in a standard CMOS process while the second IC is made using processes that support higher switching rates. The first IC produces a source-centered double data rate forward transmit clock from a reference clock selectable from either a crystal oscillator, a voltage controlled oscillator using a loop clock from the receive side of the bit stream multiplexer or a reverse clock generated by the second IC. The reverse clock can be selected as the source of the reference either by default, or in response to a specific condition.

Abstract translation: 多级比特流多路复用器，其分割两个或多个集成电路之间的复用功能。 第一个集成电路接收16位流，产生标称数据速率为10 GBPS的4个输出位流。 第二集成电路将4个流和数据速率40GBPS的比特流复用。 第一个IC采用标准CMOS工艺制造，而第二个IC采用支持更高开关速率的工艺制造。 第一个IC从可以从晶体振荡器，使用来自位流多路复用器的接收侧的环形时钟的压控振荡器或由第二个时钟产生的反向时钟从基准时钟产生源为中心的双数据速率正向传输时钟 我知道了。 默认情况下也可以选择反向时钟作为参考源，或响应特定条件。

公开(公告)号：US20100306568A1

公开(公告)日：2010-12-02

申请号：US12857049

申请日：2010-08-16

Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC: G06F1/04

CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract translation: 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US20050156653A1

公开(公告)日：2005-07-21

申请号：US11078151

申请日：2005-03-11

Applicant: Sridevi Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

Inventor： Sridevi Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

IPC: H03K19/0185 ,  H04L7/00 ,  H03L5/00

CPC classification number: H03K19/018585 ,  H04L7/0008

Abstract: An integrated circuit includes a core circuit and a buffer circuit. The buffer circuit includes a plurality of input buffers and a plurality of output buffers that service a plurality of voltage domains on a single set of input/output lines. These voltage domains are controllable to service multiple voltage levels, consistent with various interface standards. In one construction, the core circuit operates at 1.2 volts and the buffer circuit supports both a 1.2 volts interface standard and a 3.3 volts interface standard.

Abstract translation: 集成电路包括核心电路和缓冲电路。 缓冲电路包括多个输入缓冲器和多个输出缓冲器，其在单组输入/输出线上服务多个电压域。 这些电压域是可控制的，以满足与各种接口标准一致的多个电压电平。 在一个结构中，核心电路工作在1.2伏特，缓冲电路支持1.2伏接口标准和3.3伏接口标准。

公开(公告)号：US08750338B2

公开(公告)日：2014-06-10

申请号：US13556863

申请日：2012-07-24

Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC: H04J3/02

CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract translation: 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US20120287950A1

公开(公告)日：2012-11-15

申请号：US13556863

申请日：2012-07-24

Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC: H04J3/02

CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract translation: 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US07778288B2

公开(公告)日：2010-08-17

申请号：US12014094

申请日：2008-01-15

Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC: H04J3/02

CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract translation: 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US07630410B2

公开(公告)日：2009-12-08

申请号：US10349450

申请日：2003-01-22

Applicant: Mohammad Nejad ,  Daniel Schoch

Inventor： Mohammad Nejad ,  Daniel Schoch

IPC: H04J3/04

CPC classification number: H04J3/047 ,  H04J3/0685

Abstract: A bit stream multiplexer and a bit stream demultiplexer of the present invention couples a communication Application Specific Integrate Circuit (ASIC) to a high-speed bit stream media. The bit stream multiplexer includes a first transmit data multiplexing integrated circuit having an input that receives a first plurality of bit streams at a first bit rate from the communication ASIC and an output that produces a second plurality of bit streams at a second bit rate, the second plurality having fewer bit streams than said first plurality. It further includes a second transmit data multiplexing integrated circuit having an input that receives the second plurality of bit streams at the second bit rate and an output that produces a single bit stream at a line bit rate, the single bit stream having a predetermined bit order. The bit stream demultiplexer includes similar demultiplexing integrated circuits. These circuits include an interface that may be ordered, have signal line polarities altered, or bit asserted states altered depending upon the particular implementation.

Abstract translation: 本发明的比特流多路复用器和比特流解复用器将通信专用集成电路（ASIC）耦合到高速比特流媒体。 比特流多路复用器包括第一发射数据复用集成电路，其具有从通信ASIC以第一比特率接收第一多个比特流的输入和以第二比特率产生第二多个比特流的输出， 第二多个具有比所述第一多个更少的比特流。 它还包括第二发射数据多路复用集成电路，其具有接收第二比特率的第二多个比特流的输入和以线路比特率产生单个比特流的输出，该单比特流具有预定比特顺序 。 比特流解复用器包括类似的解复用集成电路。 这些电路包括可以被排序的接口，信号线极性改变，或者根据具体实现改变位置位状态。

公开(公告)号：US07577171B2

公开(公告)日：2009-08-18

申请号：US10361463

申请日：2003-02-10

Applicant: Mohammad Nejad ,  Guangming Yin ,  Ali Ghiasi

Inventor： Mohammad Nejad ,  Guangming Yin ,  Ali Ghiasi

IPC: H04J3/02

CPC classification number: H04L5/023 ,  H04L7/0008

Abstract: A multiple bit stream interface interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit. The multiple bit stream interface includes an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate. The interface further includes a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate. The first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication ASIC at a first bit rate. The second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate. The interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines. The transmit data clock is carried on a line that is centered with respect to the first group of lines and the second group of lines such that it resides between the first group of lines and the second group of lines. The interface may also interface a first receive data demultiplexing integrated circuit and a second receive data demultiplexing integrated circuit.

Abstract translation: 多比特流接口将第一发送数据多路复用集成电路和第二发送数据多路复用集成电路接口。 多比特流接口包括多个发送比特流的接口，每个发送比特流以接口比特率携带相应的比特流。 该接口还包括以对应于接口比特率的一半的频率工作的发送数据时钟。 第一发送数据复用集成电路以第一比特率从通信ASIC接收第一多个发送比特流。 第二发送数据复用集成电路以线路比特率产生单个比特流输出。 所述多个发送比特流的接口被分成第一组和第二组，其中所述第一组在第一组线路上承载，并且所述第二组在第二组线路上承载。 发送数据时钟在相对于第一组线路和第二组线路居中的线路上承载，使得它位于第一组线路组与第二组线路组之间。 接口还可以将第一接收数据解复用集成电路和第二接收数据解复用集成电路接口。

公开(公告)号：US07349450B2

公开(公告)日：2008-03-25

申请号：US10602226

申请日：2003-06-24

Applicant: Ali Ghiasi ,  Mohammad Nejad ,  Rajagopal Anantha Rao

Inventor： Ali Ghiasi ,  Mohammad Nejad ,  Rajagopal Anantha Rao

IPC: H04J3/22

CPC classification number: H04J3/0688

Abstract: A bit stream demultiplexer that couples a high-speed bit stream media to a communication Application Specific Integrated Circuit (ASIC). The bit stream multiplexer performs its demultiplexing function staged within at least two integrated circuits. The first Integrated Circuit (IC) receives a first bit stream and performs a first demultiplexing function. A second IC performs a second demultiplexing function. The second IC acts as either a slave or a master to the first IC. In a slave mode, the second IC depends upon a transmit data clock from the first IC for latching bit stream data received from the first IC. When the second IC operates in the master mode, the second IC uses the transmit data clock from first IC as a reference input for a PLL to generate a Receive Data Clock. If an LOL or LOS occurs within the first IC, a signal to the second IC indicates these conditions causing the second IC to switch to a local oscillator reference clock to generate the Receive Data Clock.

Abstract translation: 将高速比特流媒体耦合到通信专用集成电路（ASIC）的比特流解复用器。 比特流多路复用器在至少两个集成电路中执行其解复用功能。 第一集成电路（IC）接收第一比特流并执行第一解复用功能。 第二IC执行第二解复用功能。 第二个IC作为第一个IC的从机或主机。 在从模式中，第二IC取决于来自第一IC的发送数据时钟，用于锁存从第一IC接收的比特流数据。 当第二IC在主模式下工作时，第二IC使用来自第一IC的发送数据时钟作为PLL的参考输入，以产生接收数据时钟。 如果在第一IC内出现LOL或LOS，则向第二IC发出的信号表示这些条件，使得第二IC切换到本地振荡器参考时钟以产生接收数据时钟。

公开(公告)号：US07346082B2

公开(公告)日：2008-03-18

申请号：US10361255

申请日：2003-02-10

Applicant: Ali Ghiasi ,  Mohammad Nejad ,  Guangming Yin

Inventor： Ali Ghiasi ,  Mohammad Nejad ,  Guangming Yin

IPC: H04J3/02

CPC classification number: H04J3/047 ,  H04J3/0685

Abstract: A multiple bit stream interface interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit. The multiple bit stream interface includes an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate and in a natural order. The interface further includes a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate. The first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication ASIC at a first bit rate. The second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate. The interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines. The transmit data clock is carried on a line that is centered with respect to the first group of lines and the second group of lines such that it resides between the first group of lines and the second group of lines. The interface may also interface a first receive data demultiplexing integrated circuit and a second receive data demultiplexing integrated circuit.

Abstract translation: 多比特流接口将第一发送数据多路复用集成电路和第二发送数据多路复用集成电路接口。 多比特流接口包括多个发送比特流的接口，每个发送比特流以接口比特率和自然顺序携带相应的比特流。 该接口还包括以对应于接口比特率的一半的频率工作的发送数据时钟。 第一发送数据复用集成电路以第一比特率从通信ASIC接收第一多个发送比特流。 第二发送数据复用集成电路以线路比特率产生单个比特流输出。 所述多个发送比特流的接口被分成第一组和第二组，其中所述第一组在第一组线路上承载，并且所述第二组在第二组线路上承载。 发送数据时钟在相对于第一组线路和第二组线路居中的线路上承载，使得它位于第一组线路组和第二组线路组之间。 接口还可以将第一接收数据解复用集成电路和第二接收数据解复用集成电路接口。