公开(公告)号：US20050156653A1

公开(公告)日：2005-07-21

申请号：US11078151

申请日：2005-03-11

申请人： Sridevi Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

发明人： Sridevi Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

IPC分类号： H03K19/0185 ,  H04L7/00 ,  H03L5/00

CPC分类号： H03K19/018585 ,  H04L7/0008

摘要： An integrated circuit includes a core circuit and a buffer circuit. The buffer circuit includes a plurality of input buffers and a plurality of output buffers that service a plurality of voltage domains on a single set of input/output lines. These voltage domains are controllable to service multiple voltage levels, consistent with various interface standards. In one construction, the core circuit operates at 1.2 volts and the buffer circuit supports both a 1.2 volts interface standard and a 3.3 volts interface standard.

摘要翻译： 集成电路包括核心电路和缓冲电路。 缓冲电路包括多个输入缓冲器和多个输出缓冲器，其在单组输入/输出线上服务多个电压域。 这些电压域是可控制的，以满足与各种接口标准一致的多个电压电平。 在一个结构中，核心电路工作在1.2伏特，缓冲电路支持1.2伏接口标准和3.3伏接口标准。

公开(公告)号：US07630410B2

公开(公告)日：2009-12-08

申请号：US10349450

申请日：2003-01-22

申请人： Mohammad Nejad ,  Daniel Schoch

发明人： Mohammad Nejad ,  Daniel Schoch

IPC分类号： H04J3/04

CPC分类号： H04J3/047 ,  H04J3/0685

摘要： A bit stream multiplexer and a bit stream demultiplexer of the present invention couples a communication Application Specific Integrate Circuit (ASIC) to a high-speed bit stream media. The bit stream multiplexer includes a first transmit data multiplexing integrated circuit having an input that receives a first plurality of bit streams at a first bit rate from the communication ASIC and an output that produces a second plurality of bit streams at a second bit rate, the second plurality having fewer bit streams than said first plurality. It further includes a second transmit data multiplexing integrated circuit having an input that receives the second plurality of bit streams at the second bit rate and an output that produces a single bit stream at a line bit rate, the single bit stream having a predetermined bit order. The bit stream demultiplexer includes similar demultiplexing integrated circuits. These circuits include an interface that may be ordered, have signal line polarities altered, or bit asserted states altered depending upon the particular implementation.

摘要翻译： 本发明的比特流多路复用器和比特流解复用器将通信专用集成电路（ASIC）耦合到高速比特流媒体。 比特流多路复用器包括第一发射数据复用集成电路，其具有从通信ASIC以第一比特率接收第一多个比特流的输入和以第二比特率产生第二多个比特流的输出， 第二多个具有比所述第一多个更少的比特流。 它还包括第二发射数据多路复用集成电路，其具有接收第二比特率的第二多个比特流的输入和以线路比特率产生单个比特流的输出，该单比特流具有预定比特顺序 。 比特流解复用器包括类似的解复用集成电路。 这些电路包括可以被排序的接口，信号线极性改变，或者根据具体实现改变位置位状态。

公开(公告)号：US07098692B2

公开(公告)日：2006-08-29

申请号：US11078151

申请日：2005-03-11

申请人： Sridevi R. Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

发明人： Sridevi R. Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

IPC分类号： H03K19/0175

CPC分类号： H03K19/018585 ,  H04L7/0008

摘要： An integrated circuit includes a core circuit and a buffer circuit. The buffer circuit includes a plurality of input buffers and a plurality of output buffers that service a plurality of voltage domains on a single set of input/output lines. These voltage domains are controllable to service multiple voltage levels, consistent with various interface standards. In one construction, the core circuit operates at 1.2 volts and the buffer circuit supports both a 1.2 volts interface standard and a 3.3 volts interface standard.

摘要翻译： 集成电路包括核心电路和缓冲电路。 缓冲电路包括多个输入缓冲器和多个输出缓冲器，其在单组输入/输出线上服务多个电压域。 这些电压域是可控制的，以满足与各种接口标准一致的多个电压电平。 在一个结构中，核心电路工作在1.2伏特，缓冲电路支持1.2伏接口标准和3.3伏接口标准。

公开(公告)号：US06943587B2

公开(公告)日：2005-09-13

申请号：US10448640

申请日：2003-05-30

申请人： Sridevi R. Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

发明人： Sridevi R. Joshi ,  Guangming Yin ,  Mohammad Nejad ,  Daniel Schoch

IPC分类号： H03K19/0185 ,  H04L7/00 ,  H03K19/0175

CPC分类号： H03K19/018585 ,  H04L7/0008

摘要： An integrated circuit includes a core circuit and a buffer circuit. The buffer circuit includes a plurality of input buffers and a plurality of output buffers that service a plurality of voltage domains on a single set of input/output lines. These voltage domains are controllable to service multiple voltage levels, consistent with various interface standards. In one construction, the core circuit operates at 1.2 volts and the buffer circuit supports both a 1.2 volts interface standard and a 3.3 volts interface standard.

摘要翻译： 集成电路包括核心电路和缓冲电路。 缓冲电路包括多个输入缓冲器和多个输出缓冲器，其在单组输入/输出线上服务多个电压域。 这些电压域是可控制的，以满足与各种接口标准一致的多个电压电平。 在一个结构中，核心电路工作在1.2伏特，缓冲电路支持1.2伏接口标准和3.3伏接口标准。

公开(公告)号：US20060016233A1

公开(公告)日：2006-01-26

申请号：US10899374

申请日：2004-07-23

申请人： Daniel Schoch

发明人： Daniel Schoch

IPC分类号： B21D55/00

CPC分类号： B30B15/28 ,  B21D55/00

摘要： A die monitoring system for use in a press machine includes a die element, a vibration severity monitor, and a monitor receiving portion. The vibration severity monitor is configured for monitoring a vibration severity condition of the die element. The monitor receiving portion is associated with the die element and includes a monitor cavity. This monitor cavity is configured for an operable mounting of the vibration severity monitor therewithin. A primary feature of the vibration severity monitor is that it can remain with a particular die throughout the lifetime thereof, even if the die is interchanged between machine presses.

摘要翻译： 用于冲压机的模具监控系统包括模具元件，振动强度监视器和监视器接收部分。 振动严重度监视器被配置用于监视模具元件的振动严重性条件。 显示器接收部分与模具元件相关联并且包括监视器腔。 该监视器空腔被构造成用于可操作地安装振动严重度监视器。 振动严重度监视器的主要特征是，即使在机器压力机之间互换模具，它也可以在整个寿命期间保留在特定的模具上。

公开(公告)号：US07672340B2

公开(公告)日：2010-03-02

申请号：US10349560

申请日：2003-01-23

申请人： Daniel Schoch ,  Ichiro Fujimori

发明人： Daniel Schoch ,  Ichiro Fujimori

IPC分类号： H04J3/04

CPC分类号： G01R31/31723 ,  G01R31/3187 ,  H04J3/14 ,  H04L1/243

摘要： A bit stream multiplexer includes an input ordering block, a plurality of multiplexers, an output ordering block, and a Pseudo Random Bit Stream (PRBS) function. The input ordering block is operates to receive a first plurality of transmit bit streams at a first bit rate, order the first plurality of transmit bit streams based upon a first order select signal, and produce a first plurality of ordered transmit bit streams at the first bit rate. The input ordering block may also deskew the first plurality of transmit bit streams. The plurality of multiplexers operate to receive the first plurality of ordered transmit bit streams at the first bit rate and produce an interface plurality of transmit bit streams at an interface bit rate. The output ordering block operates to order the interface plurality of transmit bit streams based upon an interface order select signal. The PRBS function produces a PRBS that is coupled to at least one of the interface plurality of transmit bit streams. A bit stream demultiplexer is similarly constructed.

摘要翻译： 比特流多路复用器包括输入排序块，多个多路复用器，输出排序块和伪随机比特流（PRBS）功能。 输入排序块用于以第一比特率接收第一多个发送比特流，基于第一阶选择信号对第一多个发送比特流进行排序，并且在第一比特流产生第一多个有序发送比特流 比特率。 输入排序块还可能使第一多个发送比特流偏斜。 多个多路复用器操作以第一比特率接收第一多个有序发送比特流，并以接口比特率产生多个发送比特流的接口。 输出排序块基于接口顺序选择信号进行操作以对接口多个发送位流进行排序。 PRBS功能产生耦合到至少一个接收多个发送比特流的PRBS。 类似地构造位流解复用器。

公开(公告)号：US20060288250A1

公开(公告)日：2006-12-21

申请号：US11474681

申请日：2006-06-26

申请人： Daniel Schoch

发明人： Daniel Schoch

IPC分类号： G06F1/04

CPC分类号： G06F1/04 ,  H03L7/0814 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

摘要： A low-speed DLL facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected. The phase chosen is that which eliminates any difference in the phases of the 156 MHz clock that clocks the data transmitted to the ASIC domain and the clock that is used in the ASIC domain to latch the data. Thus, the interpolator takes advantage of the availability of the high-speed clock to generate a sufficient number of phases for a low speed DLL.

公开(公告)号：US06356124B1

公开(公告)日：2002-03-12

申请号：US09603042

申请日：2000-06-26

申请人： Daniel Schoch

发明人： Daniel Schoch

IPC分类号： H03B2100

CPC分类号： G06F1/0321

摘要： A signal generator is disclosed. The signal generator includes a variable frequency selector that is configured to provide a variable frequency for generation of a variable frequency signal. The signal generator also includes a periodic signal generator. The periodic signal generator is used to generate a periodic signal. The periodic signal generator has an input receiving the variable frequency signal and an output providing the periodic signal. The periodic signal has a frequency approximately the same as the variable frequency selection. The periodic signal generator stores a table of values associated with a reference periodic signal, each stored value corresponding to a discrete time in the reference periodic signal. The periodic signal generator is configured to interpolate between the discrete points in the table of derivative values.

摘要翻译： 公开了一种信号发生器。 信号发生器包括可变频率选择器，其被配置为提供用于产生可变频率信号的可变频率。 信号发生器还包括周期信号发生器。 周期信号发生器用于产生周期信号。 周期信号发生器具有接收可变频率信号的输入端和提供周期信号的输出。 周期信号具有与可变频率选择大致相同的频率。 周期信号发生器存储与参考周期信号相关联的值的表，每个存储的值对应于参考周期信号中的离散时间。 周期信号发生器被配置为在导数值表中的离散点之间插值。

公开(公告)号：US07334153B2

公开(公告)日：2008-02-19

申请号：US11738913

申请日：2007-04-23

申请人： Daniel Schoch

发明人： Daniel Schoch

IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F1/00

CPC分类号： G06F1/04 ,  H03L7/0814 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

摘要： A low-speed delay locked loop (DLL) facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected. The phase chosen is that which eliminates any difference in the phases of the 156 MHz clock that clocks the data transmitted to the ASIC domain and the clock that is used in the ASIC domain to latch the data. Thus, the interpolator takes advantage of the availability of the high-speed clock to generate a sufficient number of phases for a low speed DLL.

摘要翻译： 低速延迟锁定环（DLL）有助于将高速RX数据解复用器电路直接与专用集成电路（ASIC）之间的偏斜校准接口，通过将156 MHz ASIC时钟锁定到156 MHz参考电压 源自高速2.5 GHz时钟。 该DLL使用数字内插器来产生156MHz时钟的32个相位。 数字内插器使用带循环反馈的双时钟移位寄存器提供相位。 移位寄存器使用2.5 GHz时钟双倍时钟。 寄存器输出被抽头并馈送到具有由DLL产生的相位差信号控制的相位选择输入的32:1复用器。 相位差控制信号被转换成其幅度的数字表示，借此可以选择所需数量的相移增量。 所选择的相位是消除156MHz时钟的时钟相位的任何差异，该时钟将ASIC发送到ASIC域的数据和在ASIC域中使用的时钟来锁存数据。 因此，内插器利用高速时钟的可用性来产生用于低速DLL的足够数量的相位。

公开(公告)号：US20050131651A1

公开(公告)日：2005-06-16

申请号：US11046961

申请日：2005-01-31

申请人： Daniel Schoch ,  Titus Broek

发明人： Daniel Schoch ,  Titus Broek

IPC分类号： B30B15/00 ,  G01R13/00

CPC分类号： B30B15/0094

摘要： An apparatus and method for monitoring the force severity of a mechanical press without utilizing a contact force sensor. The method continually computes values of dynamic deflection for the press being monitored and utilizes these values to compute load on the press at any point in time.

摘要翻译： 一种用于在不使用接触力传感器的情况下监测机械压力的力的严重性的装置和方法。 该方法持续计算被监测的压力机的动态偏转值，并利用这些值在任何时间点计算压机上的载荷。