公开(公告)号：US20080018509A1

公开(公告)日：2008-01-24

申请号：US11761746

申请日：2007-06-12

Applicant: Morgan Colmer

Inventor： Morgan Colmer

IPC: H03M3/02

CPC classification number: H03M3/484 ,  H03M3/456

Abstract: A sigma-delta modulator for forming a digital output signal representative of the magnitude of an analog input signal, the modulator comprising a modulation unit comprising: a summation unit for summing the analog input signal with an adjustment signal to form a summation output signal; an integrator arranged to receive the summation output signal and form an integrator output signal dependent thereon; and a quantizer arranged to receive the integrator output signal and form the digital output signal dependent thereon; the sigma-delta modulator further comprising a feedback loop for generating the adjustment signal and comprising a selection circuit arranged to form the adjustment signal by selecting between one of two boundary values for the adjustment signal, the selection being performed in dependence on the digital output signal.

Abstract translation: 一种用于形成表示模拟输入信号幅度的数字输出信号的Σ-Δ调制器，所述调制器包括：调制单元，包括：求和单元，用于将所述模拟输入信号与调整信号相加以形成求和输出信号; 积分器，被布置成接收所述求和输出信号并形成依赖于其的积分器输出信号; 以及量化器，被布置成接收积分器输出信号并形成依赖于其的数字输出信号; 所述Σ-Δ调制器还包括用于产生所述调整信号的反馈回路，并且包括选择电路，所述选择电路经布置以通过在所述调整信号的两个边界值中的一个之间进行选择来形成所述调整信号，所述选择根据所述数字输出信号 。

公开(公告)号：US08140939B2

公开(公告)日：2012-03-20

申请号：US11913259

申请日：2006-07-06

Applicant: Morgan Colmer ,  Robert Macaulay

Inventor： Morgan Colmer ,  Robert Macaulay

IPC: G11C29/00

CPC classification number: G06F11/1068

Abstract: A data processing device for detecting and correcting data errors of a re-writable memory via an error correction algorithm. In one embodiment, the data processing device includes a coding unit implemented in hardware and an error correction unit implemented in software. In one embodiment, the coding unit is capable receiving a first set of data to be written to the memory and processing that data in accordance with an error correction algorithm to form a second set of data. The second set of data may be output to memory. In one embodiment, the coding unit receives data from the memory and processes that data in accordance with the error correction algorithm to determine whether the data contains an error. In one embodiment, the error correction unit receives data that contains an error and produces corrected data via an error correction algorithm. The corrected data may be output to the memory.

Abstract translation: 一种用于通过纠错算法检测和校正可重写存储器的数据错误的数据处理装置。 在一个实施例中，数据处理装置包括以硬件实现的编码单元和以软件实现的纠错单元。 在一个实施例中，编码单元能够接收要写入存储器的第一组数据并根据纠错算法处理该数据以形成第二组数据。 第二组数据可以被输出到存储器。 在一个实施例中，编码单元从存储器接收数据并根据纠错算法处理该数据以确定数据是否包含错误。 在一个实施例中，纠错单元接收包含错误的数据，并通过纠错算法产生校正数据。 校正的数据可以被输出到存储器。

公开(公告)号：US20080235560A1

公开(公告)日：2008-09-25

申请号：US11913259

申请日：2006-07-06

Applicant: Morgan Colmer ,  Robert Macaulay

Inventor： Morgan Colmer ,  Robert Macaulay

IPC: G06F11/10

CPC classification number: G06F11/1068

Abstract: A data processing device for detecting and correcting data errors of a re-writable memory via an error correction algorithm. In one embodiment, the data processing device includes a coding unit implemented in hardware and an error correction unit implemented in software. In one embodiment, the coding unit is capable receiving a first set of data to be written to the memory and processing that data in accordance with an error correction algorithm to form a second set of data. The second set of data may be output to memory. In one embodiment, the coding unit receives data from the memory and processes that data in accordance with the error correction algorithm to determine whether the data contains an error. In one embodiment, the error correction unit receives data that contains an error and produces corrected data via an error correction algorithm. The corrected data may be output to the memory.

Abstract translation: 一种用于通过纠错算法检测和校正可重写存储器的数据错误的数据处理装置。 在一个实施例中，数据处理装置包括以硬件实现的编码单元和以软件实现的纠错单元。 在一个实施例中，编码单元能够接收要写入存储器的第一组数据并根据纠错算法处理该数据以形成第二组数据。 第二组数据可以被输出到存储器。 在一个实施例中，编码单元从存储器接收数据并根据纠错算法处理该数据以确定数据是否包含错误。 在一个实施例中，纠错单元接收包含错误的数据，并通过纠错算法产生校正数据。 校正的数据可以被输出到存储器。

公开(公告)号：US20100291889A1

公开(公告)日：2010-11-18

申请号：US12160775

申请日：2006-05-22

Applicant: Morgan Colmer ,  Christoper Whitehouse ,  Martin Bastin

Inventor： Morgan Colmer ,  Christoper Whitehouse ,  Martin Bastin

IPC: H04B1/18

CPC classification number: H03J1/0075

Abstract: A radio comprising a receiver for receiving signals comprising a plurality of signal components of different carrier frequencies and a tuner for selecting a signal component of a particular carrier frequency from the plurality of received signal components, the radio having a user interface comprising a user input component and the radio being configured to cause the tuner to operate in a first tuning mode when the user input component is activated for less than a first period of time, operate in a second tuning mode when the user input component is activated for longer than the first period of time and less than a second period of time and operate in a third tuning mode when the user input component is activated for at least the second period of time.

Abstract translation: 一种无线电设备，包括用于接收包括不同载波频率的多个信号分量的信号的接收机和用于从所述多个接收信号分量中选择特定载波频率的信号分量的调谐器，所述无线电装置具有包括用户输入部件 并且所述无线电装置被配置为当所述用户输入组件被激活少于第一时间段时使所述调谐器在第一调谐模式下操作，当所述用户输入组件被激活长于所述第一调谐模式 时间段并且小于第二时间段，并且当用户输入组件被激活至少第二时间段时，以第三调谐模式操作。

公开(公告)号：US20080104156A1

公开(公告)日：2008-05-01

申请号：US11851697

申请日：2007-09-07

Applicant: Rob Macaulay ,  Morgan Colmer

Inventor： Rob Macaulay ,  Morgan Colmer

IPC: G06F7/58

CPC classification number: G06F7/588 ,  H03M3/348 ,  H03M3/43 ,  H03M3/456

Abstract: A random number generator comprising a sigma-delta modulator, the sigma-delta modulator having a modulation unit and a feedback loop arranged to receive a digital output signal from the modulator and form an adjustment signal in dependence on the digital output signal such that at any given time the absolute difference between an amplitude of a summation output signal of the modulator and a quantizer threshold of the modulator is less than the first voltage range. The random number generator is thus capable of forming a digital output signal that has a high degree of entropy.

Abstract translation: 一种随机数发生器，包括Σ-Δ调制器，具有调制单元的Σ-Δ调制器和布置成从调制器接收数字输出信号并根据数字输出信号形成调整信号的反馈环路， 给定时间时，调制器的求和输出信号的幅度与调制器的量化器阈值之间的绝对差小于第一电压范围。 因此，随机数发生器能够形成具有高度熵的数字输出信号。

公开(公告)号：US07958174B2

公开(公告)日：2011-06-07

申请号：US11851697

申请日：2007-09-07

Applicant: Rob Macaulay ,  Morgan Colmer

Inventor： Rob Macaulay ,  Morgan Colmer

IPC: G06F7/58

CPC classification number: G06F7/588 ,  H03M3/348 ,  H03M3/43 ,  H03M3/456

Abstract: A random number generator comprising a sigma-delta modulator, the sigma-delta modulator having a modulation unit and a feedback loop arranged to receive a digital output signal from the modulator and form an adjustment signal in dependence on the digital output signal such that at any given time the absolute difference between an amplitude of a summation output signal of the modulator and a quantizer threshold of the modulator is less than the first voltage range. The random number generator is thus capable of forming a digital output signal that has a high degree of entropy.

Abstract translation: 一种随机数发生器，包括Σ-Δ调制器，具有调制单元的Σ-Δ调制器和布置成从调制器接收数字输出信号并根据数字输出信号形成调整信号的反馈环路， 给定时间时，调制器的求和输出信号的幅度与调制器的量化器阈值之间的绝对差小于第一电压范围。 因此，随机数发生器能够形成具有高度熵的数字输出信号。