公开(公告)号：US08484448B2

公开(公告)日：2013-07-09

申请号：US13399023

申请日：2012-02-17

申请人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

发明人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

IPC分类号： G06F9/00 ,  G06F15/177

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

摘要： Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.

摘要翻译： 信息处理系统，包括具有低于第一操作电流的第一操作模式和第二操作模式，当引导地址寄存器从第二操作模式返回到第一操作模式时，首先保存由处理单元执行的指令的地址的寄存器，其中该地址为 当第二至第一操作模式转换时，输出到处理单元，其中引导地址寄存器是可重写的，信息保持电路保持外围电路模块寄存器的值，其中信息保持电路在第二操作模式中保持关于 外围电路模块寄存器，并且将关于第二至第一操作模式移位的信息保持电路中保存的信息传送到外围电路模块寄存器，并且其中当在第二操作模式中从系统外部发布中断请求时 信息处理系统执行与内部相对应的中断处理 破产请求

公开(公告)号：US20120151197A1

公开(公告)日：2012-06-14

申请号：US13399023

申请日：2012-02-17

申请人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

发明人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

IPC分类号： G06F9/00

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

摘要： Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.

摘要翻译： 信息处理系统，包括具有低于第一操作电流的第一操作模式和第二操作模式，当引导地址寄存器从第二操作模式返回到第一操作模式时，首先保存由处理单元执行的指令的地址的寄存器，其中该地址为 当第二至第一操作模式转换时，输出到处理单元，其中引导地址寄存器是可重写的，信息保持电路保持外围电路模块寄存器的值，其中信息保持电路在第二操作模式中保持关于 外围电路模块寄存器，并且将关于第二至第一操作模式移位的信息保持电路中保存的信息传送到外围电路模块寄存器，并且其中当在第二操作模式中从系统外部发布中断请求时 信息处理系统执行与内部相对应的中断处理 破产请求

公开(公告)号：US20110032993A1

公开(公告)日：2011-02-10

申请号：US12934134

申请日：2009-03-16

申请人： Motokazu Ozawa ,  Takaaki Imanaka ,  Mitsunori Houki

发明人： Motokazu Ozawa ,  Takaaki Imanaka ,  Mitsunori Houki

IPC分类号： H04N7/26

CPC分类号： H04N19/523 ,  H04N19/182 ,  H04N19/433 ,  H04N19/44

摘要： An image memory access control unit (502) judges whether or not an additional pixel required for motion compensation is necessary, the additional pixel not being included in a plurality of pixels forming an image shown by a reference block. When the additional pixel is judged to be necessary, a yet-to-be-obtained-pixel interpolating unit (503) generates at least one additional pixel, and generates a reference image to be used for motion compensation using the generated at least one additional pixel and at least a part of the image shown by the reference block. When the additional pixel is judged to be unnecessary, the yet-to-be-obtained-pixel interpolating unit (503) outputs at least a part of the image shown by the reference block as the reference image.

摘要翻译： 图像存储器访问控制单元（502）判断是否需要运动补偿所需的附加像素，附加像素不包括在形成由参考块所示的图像的多个像素中。 当附加像素被判断为必需时，尚未被获得的像素内插单元（503）生成至少一个附加像素，并且使用所生成的至少一个附加的像素生成用于运动补偿的参考图像 像素和参考块所示的图像的至少一部分。 当附加像素被判定为不需要时，尚未获得的像素内插单元（503）输出由参考块所示的图像的至少一部分作为参考图像。

公开(公告)号：US20070226405A1

公开(公告)日：2007-09-27

申请号：US11703762

申请日：2007-02-08

申请人： Takao Watanabe ,  Motokazu Ozawa ,  Tomonori Sekiguchi

发明人： Takao Watanabe ,  Motokazu Ozawa ,  Tomonori Sekiguchi

IPC分类号： G06F12/00

CPC分类号： G06F12/0802 ,  G06F2212/2515 ,  G11C29/76 ,  Y02D10/13

摘要： In an information processor including memory devices such as DRAMs and others, by reducing the power consumption of memory devices and efficiently repairing defect bits, a highly reliable information processor is realized. In an information processor including an external memory such as a DRAM, a second memory whose power consumption at the access time is smaller than that of the external memory is disposed, and cache data of the external memory and repair data are stored in this second memory. To an input address given from a central processing unit via a primary cache controller, a memory controller determines a hit or a miss with reference to a tag memory for cache and a tag memory for repair, and when one or both of tag memory for cache and a tag memory for repair are hit, it accesses the second memory.

摘要翻译： 在包括诸如DRAM等存储器件的信息处理器中，通过降低存储器件的功耗并有效地修复缺陷位，实现了高度可靠的信息处理器。 在包括诸如DRAM的外部存储器的信息处理器中，设置存取时间小于外部存储器的功耗的第二存储器，并且将外部存储器和修复数据的高速缓存数据存储在该第二存储器中 。 对于通过主缓存控制器从中央处理单元给出的输入地址，存储器控制器参考用于高速缓存的标签存储器和用于修复的标签存储器以及当缓存的标签存储器中的一个或两个时，确定命中或未命中 并且用于修复的标签存储器被命中，它访问第二存储器。

公开(公告)号：US08228214B2

公开(公告)日：2012-07-24

申请号：US12844134

申请日：2010-07-27

申请人： Yuya Shigenobu ,  Motokazu Ozawa ,  Nobuo Higaki ,  Takeshi Furuta ,  Takahiro Kageyama ,  Masaki Minami

发明人： Yuya Shigenobu ,  Motokazu Ozawa ,  Nobuo Higaki ,  Takeshi Furuta ,  Takahiro Kageyama ,  Masaki Minami

IPC分类号： H03M7/40

CPC分类号： H03M7/425 ,  G10L19/167 ,  H04N19/44 ,  H04N19/91

摘要： A variable-length code decoding apparatus that decodes a bitstream includes: a storage unit that stores a variable-length code table; a bitstream cutout unit that outputs a bit string of a fixed length; a reference unit that outputs decoded data and a code length with reference to the storage unit; a determination unit that determines whether a bit string of the fixed length is accumulated; a determination unit that determines whether a bit string of a length that is shorter than the fixed length is accumulated; and a selection unit that selects one of the determination results from the determination units. The bitstream cutout unit sets a starting bit based on the selected determination result, and the selection unit switches the selection of the determination results from the determination units.

摘要翻译： 对比特流解码的可变长度码解码装置包括：存储单元，存储可变长度码表; 比特流缺口单元，输出固定长度的比特串; 参考单元，其参考存储单元输出解码数据和代码长度; 确定单元，确定是否累积了固定长度的比特串; 确定单元，其确定是否累积了长于所述固定长度的长度的比特串; 以及选择单元，其从所述确定单元中选择所述确定结果之一。 比特流切断单元基于所选择的确定结果设置起始位，并且选择单元从确定单元切换确定结果的选择。

公开(公告)号：US08122233B2

公开(公告)日：2012-02-21

申请号：US12124232

申请日：2008-05-21

申请人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

发明人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

IPC分类号： G06F9/00 ,  G06F15/177

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

摘要： An information processing device, including: a processing unit; a peripheral circuit module; and a boot address register, wherein the information processing device comprises a first operation mode and a second operation mode having an operating current which is lower than that of said first operation mode, wherein the boot address register holds an address of an instruction to be executed by said processing unit first when the boot address register returns from said second operation mode to said first operation mode, wherein the address is output from said boot address to the processing unit when said information processing device shifts from said second operation mode to said first operation mode.

摘要翻译： 一种信息处理装置，包括：处理单元; 外围电路模块; 以及引导地址寄存器，其中所述信息处理设备包括具有低于所述第一操作模式的操作电流的第一操作模式和第二操作模式，其中所述引导地址寄存器保存要执行的指令的地址 所述处理单元首先当所述引导地址寄存器从所述第二操作模式返回到所述第一操作模式时，其中当所述信息处理设备从所述第二操作模式转换到所述第一操作时，所述地址从所述引导地址输出到所述处理单元 模式。

公开(公告)号：US07809920B2

公开(公告)日：2010-10-05

申请号：US11703762

申请日：2007-02-08

申请人： Takao Watanabe ,  Motokazu Ozawa ,  Tomonori Sekiguchi

发明人： Takao Watanabe ,  Motokazu Ozawa ,  Tomonori Sekiguchi

IPC分类号： G06F12/02

CPC分类号： G06F12/0802 ,  G06F2212/2515 ,  G11C29/76 ,  Y02D10/13

摘要： In an information processor including memory devices such as DRAMs and others, by reducing the power consumption of memory devices and efficiently repairing defect bits, a highly reliable information processor is realized. In an information processor including an external memory such as a DRAM, a second memory whose power consumption at the access time is smaller than that of the external memory is disposed, and cache data of the external memory and repair data are stored in this second memory. To an input address given from a central processing unit via a primary cache controller, a memory controller determines a hit or a miss with reference to a tag memory for cache and a tag memory for repair, and when one or both of tag memory for cache and a tag memory for repair are hit, it accesses the second memory.

摘要翻译： 在包括诸如DRAM等存储器件的信息处理器中，通过降低存储器件的功耗并有效地修复缺陷位，实现了高度可靠的信息处理器。 在包括诸如DRAM的外部存储器的信息处理器中，设置存取时间小于外部存储器的功耗的第二存储器，并且将外部存储器和修复数据的高速缓存数据存储在该第二存储器中 。 对于通过主缓存控制器从中央处理单元给出的输入地址，存储器控制器参考用于高速缓存的标签存储器和用于修复的标签存储器以及当缓存的标签存储器中的一个或两个时，确定命中或未命中 并且用于修复的标签存储器被命中，它访问第二存储器。

公开(公告)号：US20080282076A1

公开(公告)日：2008-11-13

申请号：US12124232

申请日：2008-05-21

申请人： Motokazu OZAWA ,  Naohiko IRIE ,  Saneaki TAMAKI ,  Hisayoshi IDE ,  Miki HAYAKAWA

发明人： Motokazu OZAWA ,  Naohiko IRIE ,  Saneaki TAMAKI ,  Hisayoshi IDE ,  Miki HAYAKAWA

IPC分类号： G06F1/24

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

摘要： Abstract An information processing device, including: a processing unit; a peripheral circuit module; and a boot address register, wherein the information processing device comprises a first operation mode and a second operation mode having an operating current which is lower than that of said first operation mode, wherein the boot address register holds an address of an instruction to be executed by said processing unit first when the boot address register returns from said second operation mode to said first operation mode, wherein the address is output from said boot address to the processing unit when said information processing device shifts from said second operation mode to said first operation mode.

摘要翻译： 一种信息处理装置，包括：处理单元; 外围电路模块; 以及引导地址寄存器，其中所述信息处理设备包括具有低于所述第一操作模式的操作电流的第一操作模式和第二操作模式，其中所述引导地址寄存器保存要执行的指令的地址 所述处理单元首先当所述引导地址寄存器从所述第二操作模式返回到所述第一操作模式时，其中当所述信息处理设备从所述第二操作模式转换到所述第一操作时，所述地址从所述引导地址输出到所述处理单元 模式。

公开(公告)号：US20100289674A1

公开(公告)日：2010-11-18

申请号：US12844134

申请日：2010-07-27

申请人： Yuya SHIGENOBU ,  Motokazu OZAWA ,  Nobuo HIGAKI ,  Takeshi FURUTA ,  Takahiro KAGEYAMA ,  Masaki MINAMI

发明人： Yuya SHIGENOBU ,  Motokazu OZAWA ,  Nobuo HIGAKI ,  Takeshi FURUTA ,  Takahiro KAGEYAMA ,  Masaki MINAMI

IPC分类号： H03M7/40

CPC分类号： H03M7/425 ,  G10L19/167 ,  H04N19/44 ,  H04N19/91

摘要： A variable-length code decoding apparatus that decodes a bitstream includes: a storage unit that stores a variable-length code table; a bitstream cutout unit that outputs a bit string of a fixed length; a reference unit that outputs decoded data and a code length with reference to the storage unit; a determination unit that determines whether a bit string of the fixed length is accumulated; a determination unit that determines whether a bit string of a length that is shorter than the fixed length is accumulated; and a selection unit that selects one of the determination results from the determination units. The bitstream cutout unit sets a starting bit based on the selected determination result, and the selection unit switches the selection of the determination results from the determination units.

摘要翻译： 对比特流解码的可变长度码解码装置包括：存储单元，存储可变长度码表; 比特流缺口单元，输出固定长度的比特串; 参考单元，其参考存储单元输出解码数据和代码长度; 确定单元，确定是否累积了固定长度的比特串; 确定单元，其确定是否累积了长于所述固定长度的长度的比特串; 以及选择单元，其从所述确定单元中选择所述确定结果之一。 比特流切断单元基于所选择的确定结果设置起始位，并且选择单元从确定单元切换确定结果的选择。

公开(公告)号：US20100150242A1

公开(公告)日：2010-06-17

申请号：US12595328

申请日：2008-04-03

申请人： Motokazu Ozawa

发明人： Motokazu Ozawa

IPC分类号： H04N7/26

CPC分类号： H04N19/40 ,  H04N19/176 ,  H04N19/44 ,  H04N19/70 ,  H04N19/91

摘要： To reduce bandwidth in an image data decoding device including a decoding unit which obtains image data inputted into the image data decoding device and decodes the obtained image data.A decoding device (100) which decodes a bitstream of an image, includes: a code converting unit (101) which converts the bitstream inputted to the decoding device (100) into a bitstream coded using a second coding rule in which a maximum code length is shorter than in a first coding rule by which the bitstream has been coded; and an image decoder (103) which obtains the bitstream that has been converted by the code converting unit (101), and decodes the obtained bitstream.

摘要翻译： 为了减少图像数据解码装置中的带宽，该图像数据解码装置包括：解码部，其获取输入到图像数据解码装置的图像数据，对所获得的图像数据进行解码。 一种解码图像比特流的解码装置，包括：代码转换单元，其将输入到解码装置的比特流转换为使用第二编码规则编码的比特流，其中最大编码长度 比编码比特流的第一编码规则短; 以及获取由码转换单元（101）转换的比特流的图像解码器（103），并对所获得的比特流进行解码。