公开(公告)号：US5835963A

公开(公告)日：1998-11-10

申请号：US524791

申请日：1995-09-07

申请人： Shinichi Yoshioka ,  Susumu Narita ,  Ikuya Kawasaki ,  Saneaki Tamaki

发明人： Shinichi Yoshioka ,  Susumu Narita ,  Ikuya Kawasaki ,  Saneaki Tamaki

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/14 ,  G11C29/24

CPC分类号： G06F12/1054 ,  G11C29/24 ,  G06F2212/2515

摘要： A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the central processing unit. Any of the entries in the memory is accessed when the address of the entry in question in the address space is designated. With associative writing supported, data is allowed to be written to the designated address if the searched address information retained in the entry at the designated address matches the corresponding information held in the write data upon comparison. The write data is inhibited from being written to the designated address in case of a mismatch between the two kinds of information.

摘要翻译： 一种支持关联写入并包括关联存储器和中央处理单元的数据处理器，所述关联存储器被提供在由所述中央处理单元管理的地址空间中。 当指定地址空间中有问题的条目的地址时，访问存储器中的任何条目。 如果支持相关写入，则如果在指定地址的条目中保留的搜索到的地址信息与比较时写入数据中保存的相应信息相匹配，则允许将数据写入指定地址。 在两种信息不匹配的情况下，写入数据被禁止写入指定的地址。

公开(公告)号：US08484448B2

公开(公告)日：2013-07-09

申请号：US13399023

申请日：2012-02-17

申请人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

发明人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

IPC分类号： G06F9/00 ,  G06F15/177

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

摘要： Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.

摘要翻译： 信息处理系统，包括具有低于第一操作电流的第一操作模式和第二操作模式，当引导地址寄存器从第二操作模式返回到第一操作模式时，首先保存由处理单元执行的指令的地址的寄存器，其中该地址为 当第二至第一操作模式转换时，输出到处理单元，其中引导地址寄存器是可重写的，信息保持电路保持外围电路模块寄存器的值，其中信息保持电路在第二操作模式中保持关于 外围电路模块寄存器，并且将关于第二至第一操作模式移位的信息保持电路中保存的信息传送到外围电路模块寄存器，并且其中当在第二操作模式中从系统外部发布中断请求时 信息处理系统执行与内部相对应的中断处理 破产请求

公开(公告)号：US20120151197A1

公开(公告)日：2012-06-14

申请号：US13399023

申请日：2012-02-17

申请人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

发明人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

IPC分类号： G06F9/00

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

摘要： Information processing system including a first and a second operation mode with operating current lower than the first, a register holding an address of an instruction executed by a processing unit first when a boot address register returns from second to first operation mode, wherein the address is output to the processing unit when second to first operation mode shifting, wherein the boot address register is rewritable, an information holding circuit holding a value of a peripheral circuit module register, wherein the information holding circuit holds, in the second operation mode, information about the peripheral circuit module register, and, transfers information held in the information holding circuit to the peripheral circuit module register regarding a second-to-first operation mode shift, and wherein when an interrupt request is posted from outside the system in the second operation mode, the information processing system performs interrupt processing corresponding to the interrupt request.

摘要翻译： 信息处理系统，包括具有低于第一操作电流的第一操作模式和第二操作模式，当引导地址寄存器从第二操作模式返回到第一操作模式时，首先保存由处理单元执行的指令的地址的寄存器，其中该地址为 当第二至第一操作模式转换时，输出到处理单元，其中引导地址寄存器是可重写的，信息保持电路保持外围电路模块寄存器的值，其中信息保持电路在第二操作模式中保持关于 外围电路模块寄存器，并且将关于第二至第一操作模式移位的信息保持电路中保存的信息传送到外围电路模块寄存器，并且其中当在第二操作模式中从系统外部发布中断请求时 信息处理系统执行与内部相对应的中断处理 破产请求

公开(公告)号：US07286386B2

公开(公告)日：2007-10-23

申请号：US11401284

申请日：2006-04-11

申请人： Takashi Miwa ,  Yasumi Tsutsumi ,  Masahiro Ichitani ,  Takanori Hashizume ,  Masamichi Sato ,  Naozumi Morino ,  Atsushi Nakamura ,  Saneaki Tamaki ,  Ikuo Kudo

发明人： Takashi Miwa ,  Yasumi Tsutsumi ,  Masahiro Ichitani ,  Takanori Hashizume ,  Masamichi Sato ,  Naozumi Morino ,  Atsushi Nakamura ,  Saneaki Tamaki ,  Ikuo Kudo

IPC分类号： G11C5/06 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/5386 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure. Bonding leads arranged along at least one side of the substrate may include bonding leads of rectangular configuration having longer sides disposed at acute angles with respect to the side of the substrate.

摘要翻译： 半导体器件使用分别对应于分配到存储器芯片的相对的第一和第二侧的地址和数据的接合焊盘以及连接到接合引线的地址端子和数据端子分别形成有接合引线的封装基板。 半导体器件还包括地址输出电路和用于存储器访问的数据输入/输出电路和具有数据处理功能的信号处理电路。 一种半导体芯片，其具有连接到与封装基板的地址端子对应的接合引线的接合焊盘以及连接到与封装基板的数据端子相对应的接合引线的接合焊盘，并且分布在四边的两侧， 上述存储芯片以堆叠结构安装在封装基板上。 沿着衬底的至少一侧布置的接合引线可以包括具有相对于衬底的侧面以锐角设置的长边的矩形构造的接合引线。

公开(公告)号：US5796978A

公开(公告)日：1998-08-18

申请号：US524561

申请日：1995-09-07

申请人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Susumu Narita ,  Saneaki Tamaki

发明人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Susumu Narita ,  Saneaki Tamaki

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC分类号： G06F12/1036 ,  G06F12/1027 ,  G06F2212/652 ,  Y02B60/1225

摘要： A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

摘要翻译： 能够支持多个页面大小而不增加芯片占用面积或功耗的数据处理器。 用于支持虚拟存储器的该数据处理器由具有共享其索引地址的多个存储体的集合关联型高速缓存存储器构成，其中可以为每个页面设置虚拟页面大小，并且其中包括要在每个页面之间共享的TLB 多个虚拟页面以各种方式设置。 该TLB具有用于锁存一对虚拟页码和物理页号的锁存字段。 要支持的虚拟页面的最大大小设置为最小大小的两倍，并且TLB的存储区号设置为不小于前者中两个的大小。

公开(公告)号：US07380149B2

公开(公告)日：2008-05-27

申请号：US10849063

申请日：2004-05-20

申请人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

发明人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

IPC分类号： G06F1/26 ,  G06F1/24 ,  G06F1/32 ,  G06F1/04

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

摘要： A mechanism of making a low standby current caused by power off compatible with a fast return operation from a standby caused by an interrupt is realized. An information processing device has a first area that includes a central processing unit and peripheral circuit modules, a second area having information holding circuits for holding values of registers contained in the peripheral circuit modules, and a first power switch for controlling supply of a current to the first area. When the information processing device operates in a first mode, an operating current is supplied to the first area and the second area. When the information processing device operates in a second mode, the first power switch is controlled so that the supply of the current to the first area can be shut off, and the supply of the current to the second area is continued.

摘要翻译： 实现了由与中断引起的来自待机的快速返回操作兼容的断电引起的低待机电流的机制。 信息处理装置具有包括中央处理单元和外围电路模块的第一区域，具有用于保持包含在外围电路模块中的寄存器的值的信息保持电路的第二区域和用于控制向外部电路提供电流的第一电源开关 第一个区域。 当信息处理装置以第一模式操作时，工作电流被提供给第一区域和第二区域。 当信息处理装置在第二模式下操作时，控制第一电源开关，使得可以切断对第一区域的电流的供应，并且继续向第二区域供应电流。

公开(公告)号：US20060180943A1

公开(公告)日：2006-08-17

申请号：US11401284

申请日：2006-04-11

申请人： Takashi Miwa ,  Yasumi Tsutsumi ,  Masahiro Ichitani ,  Takanori Hashizume ,  Masamichi Sato ,  Naozumi Morino ,  Atsushi Nakamura ,  Saneaki Tamaki ,  Ikuo Kudo

发明人： Takashi Miwa ,  Yasumi Tsutsumi ,  Masahiro Ichitani ,  Takanori Hashizume ,  Masamichi Sato ,  Naozumi Morino ,  Atsushi Nakamura ,  Saneaki Tamaki ,  Ikuo Kudo

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/5386 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention provides a semiconductor device having a stacked structure which realizes the miniaturization of a contour size and the reduction of thickness. The present invention also provides a semiconductor device which realizes high performance and high reliability in addition to the miniaturization of the contour size. The semiconductor device uses a package substrate on which bonding leads which are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads are formed. The semiconductor device further includes an address output circuit and a data input/output circuit which are also served for memory access and a signal processing circuit having a data processing function. A semiconductor chip in which bonding pads which are connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads which are connected to the bonding leads corresponding to the data terminals of the package substrate are distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.

摘要翻译： 本发明提供一种具有层叠结构的半导体器件，其实现了轮廓尺寸的小型化和厚度的减小。 本发明还提供了除了轮廓尺寸的小型化之外还实现高性能和高可靠性的半导体器件。 半导体装置使用封装基板，在该封装基板上分别对应于分配给存储芯片的相对的第一和第二侧的地址和数据的接合焊盘形成的接合引线以及连接到接合引线的地址端子和数据端子 形成。 半导体器件还包括还用于存储器访问的地址输出电路和数据输入/输出电路以及具有数据处理功能的信号处理电路。 一种半导体芯片，其中连接到与封装基板的地址端子相对应的接合引线的接合焊盘和连接到与封装基板的数据端子对应的接合引线的接合焊盘分配到四个 侧面和上述存储芯片以堆叠结构安装在封装基板上。

公开(公告)号：US07061785B2

公开(公告)日：2006-06-13

申请号：US10606891

申请日：2003-06-27

申请人： Takashi Miwa ,  Yasumi Tsutsumi ,  Masahiro Ichitani ,  Takanori Hashizume ,  Masamichi Sato ,  Naozumi Morino ,  Atsushi Nakamura ,  Saneaki Tamaki ,  Ikuo Kudo

发明人： Takashi Miwa ,  Yasumi Tsutsumi ,  Masahiro Ichitani ,  Takanori Hashizume ,  Masamichi Sato ,  Naozumi Morino ,  Atsushi Nakamura ,  Saneaki Tamaki ,  Ikuo Kudo

IPC分类号： G11C5/06

CPC分类号： H01L25/0657 ,  H01L23/5386 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.

摘要翻译： 半导体器件使用分别对应于分配到存储器芯片的相对的第一和第二侧的地址和数据的接合焊盘以及连接到接合引线的地址端子和数据端子分别形成有接合引线的封装基板。 半导体器件还包括地址输出电路和用于存储器访问的数据输入/输出电路和具有数据处理功能的信号处理电路。 一种半导体芯片，其具有连接到与封装基板的地址端子对应的接合引线的接合焊盘以及连接到与封装基板的数据端子相对应的接合引线的接合焊盘，并且分布在四边的两侧， 上述存储芯片以堆叠结构安装在封装基板上。

公开(公告)号：US6047354A

公开(公告)日：2000-04-04

申请号：US7249

申请日：1998-01-14

申请人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Susumu Narita ,  Saneaki Tamaki

发明人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Susumu Narita ,  Saneaki Tamaki

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G11C15/00

CPC分类号： G06F12/1036 ,  G06F12/1027 ,  G06F2212/652 ,  Y02B60/1225

摘要： A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

摘要翻译： 能够支持多个页面大小而不增加芯片占用面积或功耗的数据处理器。 用于支持虚拟存储器的该数据处理器由具有共享其索引地址的多个存储体的集合关联型高速缓存存储器构成，其中可以为每个页面设置虚拟页面大小，并且其中包括要在每个页面之间共享的TLB 多个虚拟页面以各种方式设置。 该TLB具有用于锁存一对虚拟页码和物理页号的锁存字段。 要支持的虚拟页面的最大大小设置为最小大小的两倍，并且TLB的存储区号设置为不小于前者中两个的大小。

公开(公告)号：US08122233B2

公开(公告)日：2012-02-21

申请号：US12124232

申请日：2008-05-21

申请人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

发明人： Motokazu Ozawa ,  Naohiko Irie ,  Saneaki Tamaki ,  Hisayoshi Ide ,  Miki Hayakawa

IPC分类号： G06F9/00 ,  G06F15/177

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

摘要： An information processing device, including: a processing unit; a peripheral circuit module; and a boot address register, wherein the information processing device comprises a first operation mode and a second operation mode having an operating current which is lower than that of said first operation mode, wherein the boot address register holds an address of an instruction to be executed by said processing unit first when the boot address register returns from said second operation mode to said first operation mode, wherein the address is output from said boot address to the processing unit when said information processing device shifts from said second operation mode to said first operation mode.

摘要翻译： 一种信息处理装置，包括：处理单元; 外围电路模块; 以及引导地址寄存器，其中所述信息处理设备包括具有低于所述第一操作模式的操作电流的第一操作模式和第二操作模式，其中所述引导地址寄存器保存要执行的指令的地址 所述处理单元首先当所述引导地址寄存器从所述第二操作模式返回到所述第一操作模式时，其中当所述信息处理设备从所述第二操作模式转换到所述第一操作时，所述地址从所述引导地址输出到所述处理单元 模式。