公开(公告)号：US20090108302A1

公开(公告)日：2009-04-30

申请号：US11931209

申请日：2007-10-31

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

IPC分类号： H01L27/112 ,  H01L21/82

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may comprise a performance sensitive logic device and the second device may comprise a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感逻辑设备，并且第二设备可以包括产出敏感存储器设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US07993990B2

公开(公告)日：2011-08-09

申请号：US12757567

申请日：2010-04-09

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

IPC分类号： H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US20100197118A1

公开(公告)日：2010-08-05

申请号：US12757567

申请日：2010-04-09

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

IPC分类号： H01L21/20

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US07696573B2

公开(公告)日：2010-04-13

申请号：US11931209

申请日：2007-10-31

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/00

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。