公开(公告)号：US20090108302A1

公开(公告)日：2009-04-30

申请号：US11931209

申请日：2007-10-31

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

IPC分类号： H01L27/112 ,  H01L21/82

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may comprise a performance sensitive logic device and the second device may comprise a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感逻辑设备，并且第二设备可以包括产出敏感存储器设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US07696573B2

公开(公告)日：2010-04-13

申请号：US11931209

申请日：2007-10-31

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/00

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US07993990B2

公开(公告)日：2011-08-09

申请号：US12757567

申请日：2010-04-09

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

IPC分类号： H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US20100197118A1

公开(公告)日：2010-08-05

申请号：US12757567

申请日：2010-04-09

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

IPC分类号： H01L21/20

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US20080083952A1

公开(公告)日：2008-04-10

申请号：US11538963

申请日：2006-10-05

申请人： Byeong Y. Kim ,  Xiaomeng Chen ,  Judson R. Holt ,  Christopher D. Sheraw ,  Linda Black ,  Igor Peidous

发明人： Byeong Y. Kim ,  Xiaomeng Chen ,  Judson R. Holt ,  Christopher D. Sheraw ,  Linda Black ,  Igor Peidous

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.

摘要翻译： 半导体结构及其制造方法基于外延表面半导体层在具有第一晶体取向的半导体衬底上外延生长。 半导体衬底暴露在绝缘体内半导体结构内的孔内。 外延表面半导体层与绝缘体半导体结构内的具有第二结晶取向的表面半导体层交替接触或隔离。 半导体表面层相对于其下方的掩埋介电层的凹部和其上的硬掩模层提供了外延表面半导体层内的抑制的第二结晶相生长。

公开(公告)号：US07494918B2

公开(公告)日：2009-02-24

申请号：US11538963

申请日：2006-10-05

申请人： Byeong Y. Kim ,  Xiaomeng Chen ,  Judson R. Holt ,  Christopher D. Sheraw ,  Linda Black ,  Igor Peidous

发明人： Byeong Y. Kim ,  Xiaomeng Chen ,  Judson R. Holt ,  Christopher D. Sheraw ,  Linda Black ,  Igor Peidous

IPC分类号： H01L21/4763 ,  H01L29/04

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.

摘要翻译： 半导体结构及其制造方法基于外延表面半导体层在具有第一晶体取向的半导体衬底上外延生长。 半导体衬底暴露在绝缘体内半导体结构内的孔内。 外延表面半导体层与绝缘体半导体结构内的具有第二结晶取向的表面半导体层交替接触或隔离。 半导体表面层相对于其下方的掩埋介电层的凹部和其上的硬掩模层提供了外延表面半导体层内的抑制的第二结晶相生长。

公开(公告)号：US08754446B2

公开(公告)日：2014-06-17

申请号：US11468403

申请日：2006-08-30

申请人： Xiaomeng Chen ,  Shwu-Jen Jeng ,  Byeong Y. Kim ,  Hasan M. Nayfeh

发明人： Xiaomeng Chen ,  Shwu-Jen Jeng ,  Byeong Y. Kim ,  Hasan M. Nayfeh

IPC分类号： H01L29/772

CPC分类号： H01L29/7848 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

摘要： The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.

摘要翻译： 本发明涉及形成具有密封栅极氧化物层的结构的结构和方法。 该结构包括在衬底上形成的栅极氧化层和形成在栅极氧化物层上的栅极。 该结构还包括栅极的材料邻接壁并形成在栅极下方的底切之下，以保护由底切露出的栅极氧化物层的区域。 源极和漏极区域通过材料与栅极隔离。

公开(公告)号：US20090321794A1

公开(公告)日：2009-12-31

申请号：US12555350

申请日：2009-09-08

申请人： Byeong Y. Kim ,  Xiaomeng Chen ,  Yoichi Otani

发明人： Byeong Y. Kim ,  Xiaomeng Chen ,  Yoichi Otani

IPC分类号： H01L29/04

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1207

摘要： The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.

摘要翻译： 本发明涉及具有混合通道取向并由嵌入在半导体衬底中的导电连接器连接的诸如n-FET和p-FET的互补器件。 具体地，半导体衬底具有至少具有不同表面晶取向（即混合取向）的第一和第二器件区域。 n-FET形成在第一和第二器件区域中的一个处，并且p-FET形成在第一和第二器件区域中的另一个处。 n-FET和p-FET通过位于第一和第二器件区域之间的导电连接器电连接并嵌入在半导体衬底中。 优选地，介电隔离件首先设置在第一和第二器件区域之间并且凹入以在它们之间形成间隙。 然后将导电连接器形成在凹入的电介质间隔物上方的间隙中。

公开(公告)号：US20080224255A1

公开(公告)日：2008-09-18

申请号：US12111238

申请日：2008-04-29

申请人： Byeong Y. Kim ,  Munir D. Naeem ,  Frank D. Tamweber ,  Xiaomeng Chen

发明人： Byeong Y. Kim ,  Munir D. Naeem ,  Frank D. Tamweber ,  Xiaomeng Chen

IPC分类号： H01L29/00

CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

摘要： This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to the semiconductor material, followed by an etch of the semiconductor material, selective to the insulating material, and then filling any high aspect ratio gaps with a CVD oxide, and filling the remainder of the STI with an HDP oxide.

公开(公告)号：US07491623B2

公开(公告)日：2009-02-17

申请号：US11841018

申请日：2007-08-20

申请人： Xiaomeng Chen ,  Shwu-Jen Jeng ,  Byeong Y. Kim ,  Hasan M. Nayfeh

发明人： Xiaomeng Chen ,  Shwu-Jen Jeng ,  Byeong Y. Kim ,  Hasan M. Nayfeh

IPC分类号： H01L21/76

CPC分类号： H01L29/7848 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

摘要： The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.

摘要翻译： 本发明涉及形成具有密封栅极氧化物层的结构的结构和方法。 该结构包括在衬底上形成的栅极氧化层和形成在栅极氧化物层上的栅极。 该结构还包括栅极的材料邻接壁并形成在栅极下方的底切之下，以保护由底切露出的栅极氧化物层的区域。 源极和漏极区域通过材料与栅极隔离。