公开(公告)号：US07993990B2

公开(公告)日：2011-08-09

申请号：US12757567

申请日：2010-04-09

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

IPC分类号： H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US20100197118A1

公开(公告)日：2010-08-05

申请号：US12757567

申请日：2010-04-09

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

IPC分类号： H01L21/20

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US20090108302A1

公开(公告)日：2009-04-30

申请号：US11931209

申请日：2007-10-31

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

IPC分类号： H01L27/112 ,  H01L21/82

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may comprise a performance sensitive logic device and the second device may comprise a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感逻辑设备，并且第二设备可以包括产出敏感存储器设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US07696573B2

公开(公告)日：2010-04-13

申请号：US11931209

申请日：2007-10-31

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/00

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US20080083952A1

公开(公告)日：2008-04-10

申请号：US11538963

申请日：2006-10-05

申请人： Byeong Y. Kim ,  Xiaomeng Chen ,  Judson R. Holt ,  Christopher D. Sheraw ,  Linda Black ,  Igor Peidous

发明人： Byeong Y. Kim ,  Xiaomeng Chen ,  Judson R. Holt ,  Christopher D. Sheraw ,  Linda Black ,  Igor Peidous

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.

摘要翻译： 半导体结构及其制造方法基于外延表面半导体层在具有第一晶体取向的半导体衬底上外延生长。 半导体衬底暴露在绝缘体内半导体结构内的孔内。 外延表面半导体层与绝缘体半导体结构内的具有第二结晶取向的表面半导体层交替接触或隔离。 半导体表面层相对于其下方的掩埋介电层的凹部和其上的硬掩模层提供了外延表面半导体层内的抑制的第二结晶相生长。

公开(公告)号：US07494918B2

公开(公告)日：2009-02-24

申请号：US11538963

申请日：2006-10-05

申请人： Byeong Y. Kim ,  Xiaomeng Chen ,  Judson R. Holt ,  Christopher D. Sheraw ,  Linda Black ,  Igor Peidous

发明人： Byeong Y. Kim ,  Xiaomeng Chen ,  Judson R. Holt ,  Christopher D. Sheraw ,  Linda Black ,  Igor Peidous

IPC分类号： H01L21/4763 ,  H01L29/04

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.

摘要翻译： 半导体结构及其制造方法基于外延表面半导体层在具有第一晶体取向的半导体衬底上外延生长。 半导体衬底暴露在绝缘体内半导体结构内的孔内。 外延表面半导体层与绝缘体半导体结构内的具有第二结晶取向的表面半导体层交替接触或隔离。 半导体表面层相对于其下方的掩埋介电层的凹部和其上的硬掩模层提供了外延表面半导体层内的抑制的第二结晶相生长。

公开(公告)号：US08361859B2

公开(公告)日：2013-01-29

申请号：US12942289

申请日：2010-11-09

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Abhishek Dube ,  Eric C. T. Harley ,  Judson R. Holt ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Matthew W. Stoker ,  Keith H. Tabakman

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Abhishek Dube ,  Eric C. T. Harley ,  Judson R. Holt ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Matthew W. Stoker ,  Keith H. Tabakman

IPC分类号： H01L21/8238

CPC分类号： H01L29/78 ,  H01L21/28525 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.

摘要翻译： 在至少一个预制的场效应晶体管的覆盖区上形成嵌入的应变外延半导体材料，即嵌入的应力元件，该至少一个预制的场效应晶体管至少包括图案化的栅叠层，源极区和漏极区。 结果，保留嵌入的应变外延半导体材料的亚稳态，并且避免基于植入和退火的松弛机制，因为在形成嵌入的应变外延半导体材料之前执行注入和退火。

公开(公告)号：US20120112208A1

公开(公告)日：2012-05-10

申请号：US12942289

申请日：2010-11-09

申请人： THOMAS N. ADAM ,  Stephen W. Bedell ,  Abhishek Dube ,  Eric C.T. Harley ,  Judson R. Holt ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Matthew W. Stoker ,  Keith H. Tabakman

发明人： THOMAS N. ADAM ,  Stephen W. Bedell ,  Abhishek Dube ,  Eric C.T. Harley ,  Judson R. Holt ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Matthew W. Stoker ,  Keith H. Tabakman

IPC分类号： H01L29/772 ,  H01L29/24 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/28525 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.

摘要翻译： 在至少一个预制的场效应晶体管的覆盖区上形成嵌入的应变外延半导体材料，即嵌入的应力元件，该至少一个预制的场效应晶体管至少包括图案化的栅叠层，源极区和漏极区。 结果，保留嵌入的应变外延半导体材料的亚稳态，并且避免基于植入和退火的松弛机制，因为在形成嵌入的应变外延半导体材料之前执行注入和退火。

公开(公告)号：US08440547B2

公开(公告)日：2013-05-14

申请号：US12367759

申请日：2009-02-09

申请人： Stephen W. Bedell ,  Ashima B. Chakravarti ,  Michael P. Chudzik ,  Judson R. Holt ,  Dominic J. Schepis

发明人： Stephen W. Bedell ,  Ashima B. Chakravarti ,  Michael P. Chudzik ,  Judson R. Holt ,  Dominic J. Schepis

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L29/1054 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02612 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.

公开(公告)号：US08426265B2

公开(公告)日：2013-04-23

申请号：US12938457

申请日：2010-11-03

申请人： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

发明人： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823828

摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.

摘要翻译： 一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于 厚度减小 在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。