公开(公告)号：US07993990B2

公开(公告)日：2011-08-09

申请号：US12757567

申请日：2010-04-09

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

IPC分类号： H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US20100197118A1

公开(公告)日：2010-08-05

申请号：US12757567

申请日：2010-04-09

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devendra K. Sadana

IPC分类号： H01L21/20

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US20090108302A1

公开(公告)日：2009-04-30

申请号：US11931209

申请日：2007-10-31

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

IPC分类号： H01L27/112 ,  H01L21/82

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may comprise a performance sensitive logic device and the second device may comprise a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感逻辑设备，并且第二设备可以包括产出敏感存储器设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US07696573B2

公开(公告)日：2010-04-13

申请号：US11931209

申请日：2007-10-31

申请人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

发明人： Shreesh Narasimha ,  Paul David Agnello ,  Xiaomeng Chen ,  Judson R. Holt ,  Mukesh Vijay Khare ,  Byeong Y. Kim ,  Devandra K. Sadana

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/00

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207

摘要： A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.

摘要翻译： 半导体结构包括具有第一掺杂剂极性和第一晶体取向的外延表面半导体层以及具有不同的第二掺杂剂极性和不同的第二晶体取向的横向相邻的绝缘体上半导体表面半导体层。 外延表面半导体层具有缺陷的第一边缘和缺少缺陷的邻接的第二边缘。 位于外延表面半导体层内的是具有垂直于第一边缘的第一栅极的第一器件和具有垂直于第二边缘的第二栅极的第二器件。 第一设备可以包括性能敏感的逻辑设备，并且第二设备可以包括产出敏感的存储设备。 附加的半导体结构包括具有第一极性和第二晶体取向的另外的横向相邻的第二绝缘体上半导体表面半导体层，并且没有边缘缺陷，以适应屈服敏感器件。

公开(公告)号：US06809030B2

公开(公告)日：2004-10-26

申请号：US10185547

申请日：2002-06-28

申请人： Paul David Agnello ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Kirk David Peterson ,  Robert Joseph Purtell ,  Ronnen Andrew Roy ,  Jean Louise Jordan-Sweet ,  Yun Yu Wang

发明人： Paul David Agnello ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Kirk David Peterson ,  Robert Joseph Purtell ,  Ronnen Andrew Roy ,  Jean Louise Jordan-Sweet ,  Yun Yu Wang

IPC分类号： H01L2144

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.

摘要翻译： 本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。 本发明的方法包括（a）形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是含硅基体上的合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

公开(公告)号：US07081676B2

公开(公告)日：2006-07-25

申请号：US10691299

申请日：2003-10-22

申请人： Paul David Agnello ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Kirk David Peterson ,  Robert Joseph Purtell ,  Ronnen Andrew Roy ,  Jean Louise Jordan-Sweet ,  Yun Yu Wang

发明人： Paul David Agnello ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Kirk David Peterson ,  Robert Joseph Purtell ,  Ronnen Andrew Roy ,  Jean Louise Jordan-Sweet ,  Yun Yu Wang

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.

摘要翻译： 本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。 本发明的方法包括（a）在含硅基材上形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

公开(公告)号：US5796166A

公开(公告)日：1998-08-18

申请号：US668241

申请日：1996-06-21

申请人： Paul David Agnello ,  Cyril Cabral, Jr. ,  Alfred Grill ,  Christopher Vincent Jahnes ,  Thomas John Licata ,  Ronnen Andrew Roy

发明人： Paul David Agnello ,  Cyril Cabral, Jr. ,  Alfred Grill ,  Christopher Vincent Jahnes ,  Thomas John Licata ,  Ronnen Andrew Roy

IPC分类号： H01L21/28 ,  H01L21/46 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L21/28185 ,  H01L21/28061 ,  H01L21/28202 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4941 ,  H01L29/4958 ,  H01L29/513 ,  H01L29/518 ,  H01L29/94

摘要： A multilayer structure having an oxygen or dopant diffusion barrier fabricated of an electrically conductive, thermally stable material of refractory metal-silicon-nitrogen which is resistant to oxidation, prevents out-diffusion of dopants from silicon and has a wide process window wherein the refractory metal is selected from Ta, W, Nb, V, Ti, Zr, Hf, Cr and Mo.

公开(公告)号：US06440851B1

公开(公告)日：2002-08-27

申请号：US09416083

申请日：1999-10-12

申请人： Paul David Agnello ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Kirk David Peterson ,  Robert Joseph Purtell ,  Ronnen Andrew Roy ,  Jean Louise Jordan-Sweet ,  Yun Yu Wang

发明人： Paul David Agnello ,  Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Kirk David Peterson ,  Robert Joseph Purtell ,  Ronnen Andrew Roy ,  Jean Louise Jordan-Sweet ,  Yun Yu Wang

IPC分类号： H01L2144

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.

摘要翻译： 本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。 本发明的方法包括（a）在含硅基材上形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

公开(公告)号：US5897349A

公开(公告)日：1999-04-27

申请号：US652130

申请日：1996-05-23

申请人： Paul David Agnello

发明人： Paul David Agnello

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/42376 ,  H01L21/28061 ,  H01L21/823828 ,  H01L29/4925

摘要： A gate structure in a CMOS is fabricated wherein the encapsulation material is self-aligned with the gate conductor and the gate channel. The gate conductor is formed subsequent to the device doping and heat cycles for formulation of the source and drain junction, and is preferably of greater width than the gate.

摘要翻译： 制造CMOS中的栅极结构，其中封装材料与栅极导体和栅极沟道自对准。 栅极导体在器件掺杂和用于配制源极和漏极结的热循环之后形成，并且优选地具有比栅极更大的宽度。

公开(公告)号：US5776823A

公开(公告)日：1998-07-07

申请号：US646583

申请日：1996-05-08

申请人： Paul David Agnello ,  Cyril Cabral, Jr. ,  Alfred Grill ,  Christopher Vincent Jahnes ,  Thomas John Licata ,  Ronnen Andrew Roy

发明人： Paul David Agnello ,  Cyril Cabral, Jr. ,  Alfred Grill ,  Christopher Vincent Jahnes ,  Thomas John Licata ,  Ronnen Andrew Roy

IPC分类号： H01L21/28 ,  H01L21/46 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L21/28185 ,  H01L21/28061 ,  H01L21/28202 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4941 ,  H01L29/4958 ,  H01L29/513 ,  H01L29/518 ,  H01L29/94

摘要： A multilayer structure having an oxygen or dopant diffusion barrier fabricated of an electrically conductive, thermally stable material of refractory metal-silicon-nitrogen which is resistant to oxidation, prevents out-diffusion of dopants from silicon and has a wide process window wherein the refractory metal is selected from Ta, W, Nb, V, Ti, Zr, Hf, Cr and Mo.