公开(公告)号：US20120079232A1

公开(公告)日：2012-03-29

申请号：US12890585

申请日：2010-09-24

Applicant: Glenn Hinton ,  Madhavan Parthasarathy ,  Rajesh Parthasarathy ,  Muthukumar Swaminathan ,  Raj Ramanujan ,  David Zimmerman ,  Larry O. Smith ,  Adrian C. Moga ,  Scott J. Cape ,  Wayne A. Downer ,  Robert S. Chappell

Inventor： Glenn Hinton ,  Madhavan Parthasarathy ,  Rajesh Parthasarathy ,  Muthukumar Swaminathan ,  Raj Ramanujan ,  David Zimmerman ,  Larry O. Smith ,  Adrian C. Moga ,  Scott J. Cape ,  Wayne A. Downer ,  Robert S. Chappell

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/023 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/205 ,  G06F2212/651 ,  Y02D10/13

Abstract: An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory. When data is in the cold region of memory, the micro-page table engine fetches the data to the hot memory and a hot memory block is then pushed out to the cold memory area.

Abstract translation: 公开了一种装置，方法，机器可读介质和系统。 在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页面的存储器页面请求的逻辑。 该装置还包括能够存储一个或多个存储器页面地址转换的翻译后备缓冲器（TLB）。 此外，该设备还具有能够响应于TLB不存储由存储器寻呼请求引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表中执行微物理地址查找的页面未命中处理程序。 该装置还包括能够管理页面未命中处理程序标签表条目的存储器管理逻辑。 微页表引擎允许TLB作为一个代理，确定二级存储器层次结构中的数据是在存储器的热区域还是在存储器的冷区域。 当数据处于存储器的冷区域时，微页表引擎将数据读取到热存储器，然后将热存储器块推出到冷存储器区域。

公开(公告)号：US08838935B2

公开(公告)日：2014-09-16

申请号：US12890585

申请日：2010-09-24

Applicant: Glenn Hinton ,  Madhavan Parthasarathy ,  Rajesh Parthasarathy ,  Muthukumar Swaminathan ,  Raj Ramanujan ,  David Zimmerman ,  Larry O. Smith ,  Adrian C. Moga ,  Scott J. Cape ,  Wayne A. Downer ,  Robert S. Chappell

Inventor： Glenn Hinton ,  Madhavan Parthasarathy ,  Rajesh Parthasarathy ,  Muthukumar Swaminathan ,  Raj Ramanujan ,  David Zimmerman ,  Larry O. Smith ,  Adrian C. Moga ,  Scott J. Cape ,  Wayne A. Downer ,  Robert S. Chappell

IPC: G06F12/00 ,  G06F12/10 ,  G06F12/02

CPC classification number: G06F12/1027 ,  G06F12/023 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/205 ,  G06F2212/651 ,  Y02D10/13

Abstract: In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.

Abstract translation: 在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页面的存储器页面请求的逻辑。 该装置还包括能够存储一个或多个存储器页面地址转换的翻译后备缓冲器（TLB）。 此外，该设备还具有能够响应于TLB不存储由存储器寻呼请求引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表中执行微物理地址查找的页面未命中处理程序。 该装置还包括能够管理页面未命中处理程序标签表条目的存储器管理逻辑。

公开(公告)号：US20070005922A1

公开(公告)日：2007-01-04

申请号：US11173641

申请日：2005-06-30

Applicant: Muthukumar Swaminathan ,  Tessil Thomas ,  Pete Vogt

Inventor： Muthukumar Swaminathan ,  Tessil Thomas ,  Pete Vogt

IPC: G06F13/00 ,  G06F13/28

CPC classification number: G06F13/1689

Abstract: Memory control that access memory devices having different read latencies is described. In on embodiment, a memory controller may include read latency logic to identify and match received read data with read commands to the memory devices based on values indicative of the read latency for the memory devices. In another embodiment, the memories may include read delay control to insert an amount of delay into the time a memory device takes in responding to a read command.

Abstract translation: 描述访问具有不同读延迟的存储器件的存储器控​​制。 在实施例中，存储器控制器可以包括读等待时间逻辑，以基于指示存储器设备的读延迟的值来识别并将接收的读数据与读命令相匹配的存储器设备。 在另一个实施例中，存储器可以包括读延迟控制，以将一定量的延迟插入存储器设备响应于读命令的时间。