公开(公告)号：US08836008B2

公开(公告)日：2014-09-16

申请号：US13420649

申请日：2012-03-15

申请人： Mutsumi Okajima

发明人： Mutsumi Okajima

IPC分类号： H01L29/66 ,  H01L27/115 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Certain embodiments provide a semiconductor device comprising a plurality of memory cell arrays each of which includes a plurality of memory cell transistors and select transistors each of which is disposed at either end of the memory cell transistors, a diffused layer formed between a first and a second select transistors adjacent to each other, a first sidewall film formed on each of the opposed sidewalls of said first and second select transistors, a second sidewall film formed on said first sidewall film, and a conducting layer which contacts with said diffused layer. The second sidewall film covers at least part of the top surface and the side surface of said first sidewall film. The edge of said contact portion is positioned at a distance no less than the total thickness of said first and second sidewall films from the sidewalls of said first and second select transistors.

摘要翻译： 某些实施例提供了一种包括多个存储单元阵列的半导体器件，每个存储单元阵列中的每一个包括多个存储单元晶体管和选择晶体管，每个存储单元晶体管均设置在存储单元晶体管的任一端;扩散层，形成在第一和第二 选择彼此相邻的晶体管，形成在所述第一和第二选择晶体管的相对侧壁中的每一个上的第一侧壁膜，形成在所述第一侧壁膜上的第二侧壁膜，以及与所述扩散层接触的导电层。 第二侧壁膜覆盖所述第一侧壁膜的顶表面和侧表面的至少一部分。 所述接触部分的边缘位于距离所述第一和第二选择晶体管的侧壁不小于所述第一和第二侧壁膜的总厚度的距离处。

公开(公告)号：US07851305B2

公开(公告)日：2010-12-14

申请号：US11945782

申请日：2007-11-27

申请人： Mutsumi Okajima

发明人： Mutsumi Okajima

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： A method of manufacturing a NAND nonvolatile semiconductor memory which involves forming a bit line contact between adjacent select transistors of the NAND nonvolatile semiconductor memory, the method has patterning memory cells and said select transistors of said NAND nonvolatile semiconductor memory; forming a first insulating film between adjacent two of said memory cells, between said memory cells and said select transistors, and between adjacent two of said select transistors; selectively etching the first insulating film between said select transistors to form a side wall spacer on each of said select transistors; forming a second insulating film on said memory cells, said first insulating film between said memory cells, said select transistors and said side wall spacers; forming a resist pattern on said second insulating film; and simultaneously forming an opening in an insulating film and a control gate on a floating gate of each of said select transistors using said resist pattern and an opening between said adjacent select transistors using said resist pattern.

摘要翻译： 一种制造NAND非易失性半导体存储器的方法，其包括在NAND非易失性半导体存储器的相邻选择晶体管之间形成位线接触，该方法具有图形存储单元和所述NAND非易失性半导体存储器的所述选择晶体管; 在相邻的两个所述存储单元之间，在所述存储单元和所述选择晶体管之间以及相邻的所述选择晶体管之间形成第一绝缘膜; 选择性地蚀刻所述选择晶体管之间的第一绝缘膜，以在每个所述选择晶体管上形成侧壁间隔物; 在所述存储单元上形成第二绝缘膜，所述第一绝缘膜位于所述存储单元，所述选择晶体管和所述侧壁间隔物之间​​; 在所述第二绝缘膜上形成抗蚀剂图案; 并且使用所述抗蚀剂图案和使用所述抗蚀剂图案在所述相邻的选择晶体管之间的开口同时在绝缘膜和每个所述选择晶体管的浮置栅极上的控制栅极形成开口。

公开(公告)号：US20090050951A1

公开(公告)日：2009-02-26

申请号：US12193349

申请日：2008-08-18

申请人： Jungo Inaba ,  Daina Inoue ,  Mutsumi Okajima

发明人： Jungo Inaba ,  Daina Inoue ,  Mutsumi Okajima

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section, peeling the third mask layer in the L/S section and out of the L/S section, forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section, etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section Is covered with a resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains, and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section being thinned by the etching.

摘要翻译： 根据本发明的实施例的制造半导体器件的方法包括在衬底上沉积第一至第三掩模层，处理第三掩模层，处理第二掩模层，使L / S部分中的第二掩模层变薄，以及 在L / S部分之外，将L / S部分中的第三掩模层剥离出L / S部分，在L / S部分中的第二掩模层的侧壁上形成间隔物，并在L / S部分之外 在L / S部分中的第二掩模层被抗蚀剂覆盖的条件下，在L / S部分中蚀刻第二掩模层，以除去L / S部分中的第二掩模层，而第二掩模层 保留L / S部分之外的掩模层，并且通过蚀刻处理第一掩模层，使用L / S部分中的间隔物并将L / S部分和L / S部分之外的第二掩模层作为 掩模，L / S部分中的间隔物和L / S部分和第二掩模层o之外的间隔物 通过蚀刻使L / S部分变薄。

公开(公告)号：US20080093652A1

公开(公告)日：2008-04-24

申请号：US11870735

申请日：2007-10-11

申请人： Mutsumi Okajima

发明人： Mutsumi Okajima

IPC分类号： H01L27/102 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device comprising: a transistor region formed on a semiconductor substrate and having a plurality of memory cell arrays formed of a plurality of memory cell transistors and select transistors one each of which is disposed on one and the other sides of said plurality of memory cell transistors; a diffused layer formed on the surface of said semiconductor substrate between the adjacent first and a second select transistors of said memory cell arrays in said transistor region; a first sidewall film formed on each of the opposed sidewalls of said first and second select transistors adjacent to each other; a second sidewall film formed on said first sidewall film; and a conducting layer formed between said first and second select transistors, so as to contact with said diffused layer, wherein the edge of a contact portion is positioned at a distance no less than the thickness of said second sidewall film from the sidewalls of said first and second select transistors.

摘要翻译： 一种半导体器件，包括：晶体管区域，形成在半导体衬底上，并且具有由多个存储单元晶体管形成的多个存储单元阵列和选择晶体管，每个晶体管都设置在所述多个存储单元的一侧和另一侧上 晶体管 在所述晶体管区域中的所述存储单元阵列的相邻第一和第二选择晶体管之间的所述半导体衬底的表面上形成扩散层; 形成在彼此相邻的所述第一和第二选择晶体管的相对侧壁的每一个上的第一侧壁膜; 形成在所述第一侧壁膜上的第二侧壁膜; 以及形成在所述第一和第二选择晶体管之间以与所述扩散层接触的导电层，其中接触部分的边缘位于距所述第一和第二选择晶体管的侧壁的所述第二侧壁膜的厚度不小于所述第二侧壁膜的厚度 和第二选择晶体管。

公开(公告)号：US07321147B2

公开(公告)日：2008-01-22

申请号：US11332153

申请日：2006-01-17

申请人： Mutsumi Okajima

发明人： Mutsumi Okajima

IPC分类号： H01L29/94

CPC分类号： H01L27/10867 ,  H01L27/10829

摘要： A device including a trench capacitor formed in a semiconductor substrate for configuring a DRAM cell together with a cell transistor is provided. The device also includes a cell transistor including diffused regions formed in a surface of a semiconductor substrate; a trench capacitor formed in said semiconductor substrate for configuring a DRAM cell together with said cell transistor; a buried strap formed in said semiconductor substrate to connect said diffused region to said trench capacitor; and a collar insulation film formed on sides of said buried strap.

摘要翻译： 提供了一种包括形成在半导体衬底中的用于配置DRAM单元与单元晶体管的沟槽电容器的器件。 该器件还包括一个单元晶体管，其包括形成在半导体衬底的表面中的扩散区; 形成在所述半导体衬底中的沟槽电容器，用于与所述单元晶体管一起配置DRAM单元; 形成在所述半导体衬底中以将所述扩散区域连接到所述沟槽电容器的掩埋带; 以及形成在所述掩埋带的侧面上的轴环绝缘膜。

公开(公告)号：US20070187799A1

公开(公告)日：2007-08-16

申请号：US11412044

申请日：2006-04-27

申请人： Toshiharu Tanaka ,  Shinya Watanabe ,  Mutsumi Okajima

发明人： Toshiharu Tanaka ,  Shinya Watanabe ,  Mutsumi Okajima

IPC分类号： H01L29/00

CPC分类号： H01L21/76232

摘要： A method of manufacturing a semiconductor device according to an aspect of the present invention comprises: depositing an insulation film on a silicon substrate; forming element isolation regions by processing the insulation film as well as exposing the surface of the silicon substrate in the region thereof acting as active element forming regions later; and forming the active element forming regions by epitaxially growing a silicon film on the exposed surface of the silicon substrate such that the thickness thereof is larger than the short side width in the perpendicular cross section thereof as well as smaller than the dimension of the element isolation regions in the depth direction thereof.

摘要翻译： 根据本发明的一个方面的制造半导体器件的方法包括：在硅衬底上沉积绝缘膜; 通过处理绝缘膜以及使作为有源元件形成区域的区域中的硅衬底的表面露出来形成元件隔离区域; 以及通过在硅衬底的暴露表面上外延生长硅膜使其厚度大于其垂直截面中的短边宽度以及小于元件隔离的尺寸来形成有源元件形成区域 其深度方向的区域。

公开(公告)号：US20070102744A1

公开(公告)日：2007-05-10

申请号：US11332153

申请日：2006-01-17

申请人： Mutsumi Okajima

发明人： Mutsumi Okajima

IPC分类号： H01L29/94 ,  H01L21/20

CPC分类号： H01L27/10867 ,  H01L27/10829

摘要： A method of manufacturing semiconductor devices is provided. The device includes a trench capacitor formed in a semiconductor substrate for configuring a DRAM cell together with a cell transistor. The method comprises forming a trench in a semiconductor substrate; forming a collar insulation film on sidewalls of the trench, the collar insulator extending to a surface of the semiconductor substrate; forming a trench capacitor in the trench; introducing ions into a part of the collar insulation film by implanting ions of an impurity from one of slanting directions; etching off the ion-introduced part of the collar insulation film through the use of a difference in etching rate from other parts of the collar insulation film; and forming a buried strap in the trench above the trench capacitor.

摘要翻译： 提供一种制造半导体器件的方法。 该器件包括形成在半导体衬底中的沟槽电容器，用于与单元晶体管一起配置DRAM单元。 该方法包括在半导体衬底中形成沟槽; 在所述沟槽的侧壁上形成套环绝缘膜，所述套环绝缘体延伸到所述半导体衬底的表面; 在沟槽中形成沟槽电容器; 通过从倾斜方向注入杂质离子将离子引入到轴环绝缘膜的一部分中; 通过使用与轴环绝缘膜的其他部分的蚀刻速率差异来蚀刻离子引入的环形绝缘膜部分; 以及在沟槽电容器上方的沟槽中形成掩埋带。

公开(公告)号：US20120248547A1

公开(公告)日：2012-10-04

申请号：US13420649

申请日：2012-03-15

申请人： Mutsumi Okajima

发明人： Mutsumi Okajima

IPC分类号： H01L27/088

CPC分类号： H01L21/76897 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Certain embodiments provide a semiconductor device comprising a plurality of memory cell arrays each of which includes a plurality of memory cell transistors and select transistors each of which is disposed at either end of the memory cell transistors, a diffused layer formed between a first and a second select transistors adjacent to each other, a first sidewall film formed on each of the opposed sidewalls of said first and second select transistors, a second sidewall film formed on said first sidewall film, and a conducting layer which contacts with said diffused layer. The second sidewall film covers at least part of the top surface and the side surface of said first sidewall film. The edge of said contact portion is positioned at a distance no less than the total thickness of said first and second sidewall films from the sidewalls of said first and second select transistors.

摘要翻译： 某些实施例提供了一种包括多个存储单元阵列的半导体器件，每个存储单元阵列中的每一个包括多个存储单元晶体管和选择晶体管，每个存储单元晶体管均设置在存储单元晶体管的任一端;扩散层，形成在第一和第二 选择彼此相邻的晶体管，形成在所述第一和第二选择晶体管的相对侧壁中的每一个上的第一侧壁膜，形成在所述第一侧壁膜上的第二侧壁膜，以及与所述扩散层接触的导电层。 第二侧壁膜覆盖所述第一侧壁膜的顶表面和侧表面的至少一部分。 所述接触部分的边缘位于距离所述第一和第二选择晶体管的侧壁不小于所述第一和第二侧壁膜的总厚度的距离处。

公开(公告)号：US07713819B2

公开(公告)日：2010-05-11

申请号：US11790207

申请日：2007-04-24

申请人： Mutsumi Okajima

发明人： Mutsumi Okajima

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device manufacturing method includes forming a first insulating film on a semiconductor substrate, forming a first conductor film on the first insulating film, forming a second insulating film on the first conductor film, forming a first line-and-space pattern by etching the second insulating film and the first conductor film, forming a etched region etched into a second line-and-space pattern perpendicular to the first line-and-space pattern by etching the second insulating film, the first conductor film, the first insulating film, and the semiconductor substrate, burying a third insulating film in the etched region, removing the second insulating film, forming a fourth insulating film on the first conductor film and the third insulating film, forming a second conductor film on the fourth insulating film, and forming a third line-and-space pattern parallel to the first line-and-space pattern by etching the second conductor film.

摘要翻译： 一种半导体器件制造方法，包括在半导体衬底上形成第一绝缘膜，在第一绝缘膜上形成第一导体膜，在第一导体膜上形成第二绝缘膜，通过蚀刻形成第一线间距图案 第二绝缘膜和第一导体膜，通过蚀刻第二绝缘膜，第一导体膜，第一绝缘膜，第二绝缘膜和第一导体膜，形成蚀刻到与第一线间距图案垂直的第二线间距图案中的蚀刻区域， 和半导体衬底，在蚀刻区域中埋设第三绝缘膜，去除第二绝缘膜，在第一导体膜和第三绝缘膜上形成第四绝缘膜，在第四绝缘膜上形成第二导体膜，并形成 通过蚀刻第二导体膜而与第一线间距图案平行的第三线和空间图案。

公开(公告)号：US20060138526A1

公开(公告)日：2006-06-29

申请号：US11358078

申请日：2006-02-22

申请人： Mutsumi Okajima

发明人： Mutsumi Okajima

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L29/42324

摘要： Disclosed is a semiconductor device comprising a first conductive film serving as a floating gate and formed on a semiconductor film via a first gate insulating film, a second conductive film serving as a control gate and formed on the first conductive film via a second gate insulating film, and a third conductive film buried in a contact hole formed by removing a part of the second conductive film and second gate insulating film so as to reach an upper surface of the first conductive film from an upper surface of the second conductive film.

摘要翻译： 公开了一种半导体器件，其包括用作浮置栅极的第一导电膜，并且经由第一栅极绝缘膜形成在半导体膜上，第二导电膜用作控制栅极，并且经由第二栅极绝缘膜形成在第一导电膜上 以及掩埋在通过从第二导电膜的上表面去除一部分第二导电膜和第二栅极绝缘膜从而到达第一导电膜的上表面而形成的接触孔中的第三导电膜。