公开(公告)号：US20090050951A1

公开(公告)日：2009-02-26

申请号：US12193349

申请日：2008-08-18

申请人： Jungo Inaba ,  Daina Inoue ,  Mutsumi Okajima

发明人： Jungo Inaba ,  Daina Inoue ,  Mutsumi Okajima

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section, peeling the third mask layer in the L/S section and out of the L/S section, forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section, etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section Is covered with a resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains, and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section being thinned by the etching.

摘要翻译： 根据本发明的实施例的制造半导体器件的方法包括在衬底上沉积第一至第三掩模层，处理第三掩模层，处理第二掩模层，使L / S部分中的第二掩模层变薄，以及 在L / S部分之外，将L / S部分中的第三掩模层剥离出L / S部分，在L / S部分中的第二掩模层的侧壁上形成间隔物，并在L / S部分之外 在L / S部分中的第二掩模层被抗蚀剂覆盖的条件下，在L / S部分中蚀刻第二掩模层，以除去L / S部分中的第二掩模层，而第二掩模层 保留L / S部分之外的掩模层，并且通过蚀刻处理第一掩模层，使用L / S部分中的间隔物并将L / S部分和L / S部分之外的第二掩模层作为 掩模，L / S部分中的间隔物和L / S部分和第二掩模层o之外的间隔物 通过蚀刻使L / S部分变薄。

公开(公告)号：US07687387B2

公开(公告)日：2010-03-30

申请号：US12193349

申请日：2008-08-18

申请人： Jungo Inaba ,  Daina Inoue ,  Mutsumi Okajima

发明人： Jungo Inaba ,  Daina Inoue ,  Mutsumi Okajima

IPC分类号： H01L21/3205

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A method of manufacturing a semiconductor device according to an embodiment of the present invention includes depositing first to third mask layers above a substrate, processing the third mask layer, processing the second mask layer, slimming the second mask layer in an L/S section and out of the L/S section, peeling the third mask layer in the L/S section and out of the L/S section, forming spacers on sidewalls of the second mask layer in the L/S section and out of the L/S section, etching the second mask layer in the L/S section, under a condition that the second mask layer out of the L/S section is covered with a resist, to remove the second mask layer in the L/S section while the second mask layer out of the L/S section remains, and processing the first mask layer by etching, using the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section as a mask, the spacers in the L/S section and out of the L/S section and the second mask layer out of the L/S section being thinned by the etching.

摘要翻译： 根据本发明的实施例的制造半导体器件的方法包括在衬底上沉积第一至第三掩模层，处理第三掩模层，处理第二掩模层，使L / S部分中的第二掩模层变薄，以及 在L / S部分之外，将L / S部分中的第三掩模层剥离出L / S部分，在L / S部分中的第二掩模层的侧壁上形成间隔物，并在L / S部分之外 在L / S部分中的第二掩模层被抗蚀剂覆盖的条件下，在L / S部分中蚀刻第二掩模层，以除去L / S部分中的第二掩模层，而第二掩模层 保留L / S部分之外的掩模层，并且通过蚀刻处理第一掩模层，使用L / S部分中的间隔物并将L / S部分和L / S部分之外的第二掩模层作为 掩模，L / S部分中的间隔物和L / S部分和第二掩模层o之外的间隔物 通过蚀刻使L / S部分变薄。

公开(公告)号：US20110097888A1

公开(公告)日：2011-04-28

申请号：US12929125

申请日：2011-01-03

申请人： Mitsuhiro Omura ,  Satoshi Nagashima ,  Katsunori Yahashi ,  Jungo Inaba ,  Daina Inoue

发明人： Mitsuhiro Omura ,  Satoshi Nagashima ,  Katsunori Yahashi ,  Jungo Inaba ,  Daina Inoue

IPC分类号： H01L21/28

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.

摘要翻译： 半导体存储器件包括具有层叠栅结构的多个晶体管。 每个晶体管包括半导体衬底，形成在半导体衬底上的栅极绝缘体，形成在半导体衬底上的栅极绝缘体插入的下栅极，形成在下栅极上的栅极绝缘体和在下栅极上形成并硅化的上栅极 间隔绝缘体插入。 晶体管的一部分具有通过栅极间绝缘体形成的孔，以将下栅极与上栅极连接，并且还包括由绝缘体构成并形成为小于上栅极且大于上栅极上方的孔的阻挡膜以覆盖 光圈。

公开(公告)号：US08460997B2

公开(公告)日：2013-06-11

申请号：US12929125

申请日：2011-01-03

申请人： Mitsuhiro Omura ,  Satoshi Nagashima ,  Katsunori Yahashi ,  Jungo Inaba ,  Daina Inoue

发明人： Mitsuhiro Omura ,  Satoshi Nagashima ,  Katsunori Yahashi ,  Jungo Inaba ,  Daina Inoue

IPC分类号： H01L21/302

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.

摘要翻译： 半导体存储器件包括具有层叠栅结构的多个晶体管。 每个晶体管包括半导体衬底，形成在半导体衬底上的栅极绝缘体，形成在半导体衬底上的栅极绝缘体插入的下栅极，形成在下栅极上的栅极绝缘体和在下栅极上形成并硅化的上栅极 间隔绝缘体插入。 晶体管的一部分具有通过栅极间绝缘体形成的孔，以将下栅极与上栅极连接，并且还包括由绝缘体构成并形成为小于上栅极且大于上栅极上方的孔的阻挡膜以覆盖 光圈。

公开(公告)号：US20080203461A1

公开(公告)日：2008-08-28

申请号：US12034326

申请日：2008-02-20

申请人： Jungo Inaba ,  Mutsumi Okajima ,  Hiroshi Akahori

发明人： Jungo Inaba ,  Mutsumi Okajima ,  Hiroshi Akahori

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device includes first and second gate electrodes arranged adjacent to each other, an oxide film formed between the first and second gate electrodes, and a nitride film formed on control gates and upper surfaces and sidewalls of the oxide film. Each of the first and second gate electrodes has a stacked gate structure which has a first insulating film, charge storage layer, second insulating film and control gate stacked on a semiconductor substrate. The uppermost surface of the oxide film is set higher than the uppermost surface of the control gate.

摘要翻译： 半导体器件包括彼此相邻布置的第一和第二栅电极，形成在第一和第二栅电极之间的氧化膜，以及形成在氧化膜的控制栅极和上表面和侧壁上的氮化物膜。 第一和第二栅电极中的每一个具有层叠的栅极结构，其具有堆叠在半导体衬底上的第一绝缘膜，电荷存储层，第二绝缘膜和控制栅极。 氧化膜的最上表面被设定为高于控制栅极的最上表面。