公开(公告)号：US08199849B2

公开(公告)日：2012-06-12

申请号：US12487593

申请日：2009-06-18

申请人： Myeong Hoon Oh ,  Chi Hoon Shin ,  Young Woo Kim ,  Sung Nam Kim ,  Seong Woon Kim ,  Han Namgoong

发明人： Myeong Hoon Oh ,  Chi Hoon Shin ,  Young Woo Kim ,  Sung Nam Kim ,  Seong Woon Kim ,  Han Namgoong

IPC分类号： H04L25/34

CPC分类号： H04L25/4923

摘要： Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.

摘要翻译： 提供一种通过延迟不敏感数据发送方法和数据发送方法发送数据的数据发送装置。 数据发送装置和数据发送方法使用支持2相手抖动协议的延迟不敏感数据发送方式。 在数据传输期间，通过三进制编码方式将数据编码为没有空间状态的三个逻辑状态。 根据数据发送装置和数据发送方式，与现有技术的4相延迟相比，无论线长度如何，都能够将数据稳定地发送到接收机，并且在数据传输速率方面提供更优异的性能 数据传输方式。

公开(公告)号：US20120102300A1

公开(公告)日：2012-04-26

申请号：US13278385

申请日：2011-10-21

申请人： Myeong Hoon OH ,  Young Woo KIM ,  Sung Nam KIM ,  Seong Woon KIM

发明人： Myeong Hoon OH ,  Young Woo KIM ,  Sung Nam KIM ,  Seong Woon KIM

IPC分类号： G06F15/00 ,  G06F9/315

CPC分类号： G06F9/3871 ,  G06F9/3869

摘要： Disclosed are an asynchronous pipeline system, a stage, and a data transfer mechanism. The asynchronous pipeline system having a plurality of stages based on a 4-phase protocol, includes: a first stage among the plurality of stages; and a second stage among the plurality of stages connected next to the first stage, wherein the first stage transmits and the second receives bundled data and control data through an always bundled data channel and on-demand data through an on-demand data channel according to need of the second stage.

摘要翻译： 公开了异步管线系统，阶段和数据传输机制。 具有基于四相协议的多级的异步管线系统包括：多级中的第一级; 以及与第一级相邻的多级中的第二级，其中第一级发送，第二级通过始终捆绑的数据信道和按需数据信道通过按需数据信道来接收捆绑数据和控制数据，根据 需要第二阶段

公开(公告)号：US20050200388A1

公开(公告)日：2005-09-15

申请号：US11025458

申请日：2004-12-29

申请人： Dong-Soo Har ,  Myeong-Hoon Oh

发明人： Dong-Soo Har ,  Myeong-Hoon Oh

IPC分类号： H04L12/02 ,  H02M11/00

CPC分类号： H04L12/40013

摘要： The present invention relates to a delay-insensitive DI data transfer circuit based on a current-mode multiple-valued logic for transferring data regardless of a delay time of transmission according to a length of wire. The delay-insensitive data transfer circuit of the present invention, in a delay-insensitive data transfer circuit transferring an input request signal and a data signal from a data transmission unit to a data receiving unit, comprises: an encoder for outputting a signal which has been converted to current-level signals in response to voltage-level input of data signal and request signal from the data transmission unit; and a decoder for restoring the voltage-level signals from the current-level signals of the encoder, abstracting a data signal and a request signal from the restored voltage-level signals, and outputting the data signal and the request signal to the data receiving unit.

摘要翻译： 本发明涉及一种基于用于传送数据的电流模式多值逻辑的延迟不敏感的DI数据传输电路，而不管根据电线长度的传输的延迟时间如何。 本发明的延迟不敏感数据传输电路在将输入请求信号和数据信号从数据传输单元传送到数据接收单元的延迟不敏感数据传输电路中包括：编码器，用于输出具有 响应于数据信号的电压电平输入和来自数据传输单元的请求信号，被转换成电流电平信号; 以及解码器，用于从编码器的当前电平信号恢复电压电平信号，从恢复的电压电平信号中抽取数据信号和请求信号，并将数据信号和请求信号输出到数据接收单元 。

公开(公告)号：US09086897B2

公开(公告)日：2015-07-21

申请号：US13434696

申请日：2012-03-29

申请人： Myeong-Hoon Oh ,  Sun-Wook Kim ,  Dae-Won Kim ,  Seong-Woon Kim

发明人： Myeong-Hoon Oh ,  Sun-Wook Kim ,  Dae-Won Kim ,  Seong-Woon Kim

IPC分类号： G06F9/455 ,  G06F9/44 ,  G06F9/445

CPC分类号： G06F9/4445 ,  G06F9/4451 ,  G06F9/452 ,  G06F9/45533

摘要： The present invention relates to a method and an architecture capable of efficiently providing a virtual desktop service. The service architecture for the virtual desktop service includes a connection broker for performing the management of virtual machines, a server monitoring function, and a protocol coordination function. A resource pool is configured to manage software resources that are transferred to a specific virtual machine in a streaming form at a predetermined time and that are executed on the specific virtual machine and to provide provision information about the managed software resources at the request of the connection broker, in order to provide an on-demand virtual desktop service. A virtual machine infrastructure is configured to support hardware resources, generate virtual machines in which the software of the user terminal is operated, and provide the virtual machines as virtual desktops.

摘要翻译： 本发明涉及能够有效提供虚拟桌面服务的方法和架构。 虚拟桌面服务的服务架构包括用于执行虚拟机的管理的连接代理，服务器监视功能和协议协调功能。 资源池被配置为管理在预定时间以流形式传送到特定虚拟机的软件资源，并且在特定虚拟机上执行资源池，并且在连接请求下提供关于被管理软件资源的提供信息 经纪人，以提供点播虚拟桌面服务。 虚拟机基础设施被配置为支持硬件资源，生成运行用户终端软件的虚拟机，并将虚拟机提供为虚拟桌面。

公开(公告)号：US08705592B2

公开(公告)日：2014-04-22

申请号：US13554327

申请日：2012-07-20

申请人： Myeong-Hoon Oh ,  Chi-Hoon Shin ,  Sung-Nam Kim ,  Seong-Woon Kim

发明人： Myeong-Hoon Oh ,  Chi-Hoon Shin ,  Sung-Nam Kim ,  Seong-Woon Kim

IPC分类号： H04L25/00 ,  H04B3/00 ,  G01R31/08

CPC分类号： G06F17/5059

摘要： Disclosed herein are a data transmission apparatus, a data reception apparatus, and a data transmission method. The data transmission apparatus, the data reception apparatus, and the data transmission method are capable of simplifying the circuit structure of a decoder because an assumption of the time related to a request signal and a data signal is not necessary and an additional logic for generating a clock signal for the decoder is not necessary by using a Finite State Machine (FSM) logic without storing a state via a delay device.

摘要翻译： 这里公开了数据发送装置，数据接收装置和数据发送方法。 数据发送装置，数据接收装置和数据发送方法能够简化解码器的电路结构，因为与请求信号和数据信号相关的时间的假定不是必需的，并且用于生成 通过使用有限状态机（FSM）逻辑而不通过延迟器件存储状态，解码器的时钟信号不是必需的。

公开(公告)号：US08433019B2

公开(公告)日：2013-04-30

申请号：US12825919

申请日：2010-06-29

申请人： Myeong Hoon Oh ,  Seong Woon Kim

发明人： Myeong Hoon Oh ,  Seong Woon Kim

IPC分类号： H04L7/00

CPC分类号： H04L7/0008 ,  G06F1/10 ,  G06F1/12

摘要： The present invention relates to a system and an apparatus for synchronization between heterogeneous periodic clock domains, a synchronization failure detecting circuit, and a data receiving method. The synchronization system between heterogeneous periodic clock domains including a sender and a receiver operated according to heterogeneous periodic first clock and second clock, respectively, includes: a sender that outputs a prediction clock obtained by delaying the first clock for a first time; and a receiver that predicts success and failure of synchronization between the first clock and the second clock by using the prediction clock and selectively delays the second clock for a second time according to the predicted results to synchronize the second clock with the first clock.

摘要翻译： 本发明涉及异构周期性时钟域之间的同步系统和装置，同步故障检测电路和数据接收方法。 包括发送器和接收器的异步周期性时钟域之间的同步系统分别根据异构的周期性第一时钟和第二时钟操作，包括：发送器，其输出通过第一时间延迟第一时钟获得的预测时钟; 以及接收器，其通过使用所述预测时钟来预测所述第一时钟和所述第二时钟之间的同步的成功和失败，并且根据所述预测结果选择性地延迟所述第二时钟，以使所述第二时钟与所述第一时钟同步。

公开(公告)号：US07885254B2

公开(公告)日：2011-02-08

申请号：US11927972

申请日：2007-10-30

申请人： Myeong-Hoon Oh ,  Seong-Woon Kim ,  Myung-Joon Kim

发明人： Myeong-Hoon Oh ,  Seong-Woon Kim ,  Myung-Joon Kim

IPC分类号： H04L12/50 ,  H04L12/28

CPC分类号： H04L25/49 ,  H04L25/0264 ,  H04L25/4906

摘要： Provided is a delay insensitive (DI) data transfer apparatus with low power consumption. The apparatus, includes: N number of encoders configured to receive and encode input request and data signals, where each of the N number of encoders includes: a reference current source circuit configured to generate a current; and a voltage-to-current converter circuit configured to output a current having a level of 0, output the current having the level of I, and output the current having the level of 2I; and N number of decoders configured to recover the current-level signals, where each of the decoders includes: a threshold current source circuit configured to generate first and second threshold currents; an input current mirror circuit configured to differentiate the first and second threshold currents; and a current-to-voltage converter circuit configured to detect the threshold current, recover a voltage input value, and extract data and request signals.

摘要翻译： 提供具有低功耗的延迟不敏感（DI）数据传送装置。 该装置包括：N个编码器，被配置为接收和编码输入请求和数据信号，其中N个编码器中的每一个包括：参考电流源电路，被配置为产生电流; 以及电压 - 电流转换器电路，被配置为输出电平为0的电流，输出具有电平I的电流，并输出电平为2I的电流; N个解码器被配置为恢复当前电平信号，其中每个解码器包括：阈值电流源电路，被配置为产生第一和第二阈值电流; 配置成区分第一和第二阈值电流的输入电流镜电路; 以及电流 - 电压转换器电路，被配置为检测阈值电流，恢复电压输入值，并提取数据和请求信号。

公开(公告)号：US20080123765A1

公开(公告)日：2008-05-29

申请号：US11927972

申请日：2007-10-30

申请人： Myeong-Hoon OH ,  Seong-Woon KIM ,  Myung-Joon KIM

发明人： Myeong-Hoon OH ,  Seong-Woon KIM ,  Myung-Joon KIM

IPC分类号： H04B7/02

CPC分类号： H04L25/49 ,  H04L25/0264 ,  H04L25/4906

摘要： Provided is a delay insensitive (DI) data transfer apparatus with low power consumption. The apparatus, includes: N number of encoders configured to receive and encode input request and data signals, where each of the N number of encoders includes: a reference current source circuit configured to generate a current; and a voltage-to-current converter circuit configured to output a current having a level of 0, output the current having the level of I, and output the current having the level of 2I; and N number of decoders configured to recover the current-level signals, where each of the decoders includes: a threshold current source circuit configured to generate first and second threshold currents; an input current mirror circuit configured to differentiate the first and second threshold currents; and a current-to-voltage converter circuit configured to detect the threshold current, recover a voltage input value, and extract data and request signals.

摘要翻译： 提供具有低功耗的延迟不敏感（DI）数据传送装置。 该装置包括：N个编码器，被配置为接收和编码输入请求和数据信号，其中N个编码器中的每一个包括：参考电流源电路，被配置为产生电流; 以及电压 - 电流转换器电路，被配置为输出电平为0的电流，输出具有电平I的电流，并输出电平为2I的电流; N个解码器被配置为恢复当前电平信号，其中每个解码器包括：阈值电流源电路，被配置为产生第一和第二阈值电流; 配置成区分第一和第二阈值电流的输入电流镜电路; 以及电流 - 电压转换器电路，被配置为检测阈值电流，恢复电压输入值，并提取数据和请求信号。

公开(公告)号：US09317295B2

公开(公告)日：2016-04-19

申请号：US13278385

申请日：2011-10-21

申请人： Myeong Hoon Oh ,  Young Woo Kim ,  Sung Nam Kim ,  Seong Woon Kim

发明人： Myeong Hoon Oh ,  Young Woo Kim ,  Sung Nam Kim ,  Seong Woon Kim

IPC分类号： G06F9/38

CPC分类号： G06F9/3871 ,  G06F9/3869

摘要： Disclosed are an asynchronous pipeline system, a stage, and a data transfer mechanism. The asynchronous pipeline system having a plurality of stages based on a 4-phase protocol, includes: a first stage among the plurality of stages; and a second stage among the plurality of stages connected next to the first stage, wherein the first stage transmits and the second receives bundled data and control data through an always bundled data channel and on-demand data through an on-demand data channel according to need of the second stage.

摘要翻译： 公开了异步管线系统，阶段和数据传输机制。 具有基于四相协议的多级的异步管线系统包括：多级中的第一级; 以及与第一级相邻的多级中的第二级，其中第一级发送，第二级通过始终捆绑的数据信道和按需数据信道通过按需数据信道来接收捆绑数据和控制数据，根据 需要第二阶段

公开(公告)号：US20130259166A1

公开(公告)日：2013-10-03

申请号：US13554327

申请日：2012-07-20

申请人： Myeong-Hoon Oh ,  Chi-Hoon Shin ,  Sung-Han Kim ,  Seong-Woon Kim

发明人： Myeong-Hoon Oh ,  Chi-Hoon Shin ,  Sung-Han Kim ,  Seong-Woon Kim

IPC分类号： H04B1/04 ,  H04B1/16

CPC分类号： G06F17/5059

摘要： Disclosed herein are a data transmission apparatus, a data reception apparatus, and a data transmission method. The data transmission apparatus, the data reception apparatus, and the data transmission method are capable of simplifying the circuit structure of a decoder because an assumption of the time related to a request signal and a data signal is not necessary and an additional logic for generating a clock signal for the decoder is not necessary by using a Finite State Machine (FSM) logic without storing a state via a delay device.

摘要翻译： 这里公开了数据发送装置，数据接收装置和数据发送方法。 数据发送装置，数据接收装置和数据发送方法能够简化解码器的电路结构，因为与请求信号和数据信号相关的时间的假定不是必需的，并且用于生成 通过使用有限状态机（FSM）逻辑而不通过延迟器件存储状态，解码器的时钟信号不是必需的。