公开(公告)号：US08179736B2

公开(公告)日：2012-05-15

申请号：US12654282

申请日：2009-12-16

申请人： Nam-Kyun Tak ,  Ki-Whan Song

发明人： Nam-Kyun Tak ,  Ki-Whan Song

IPC分类号： G11C17/18

CPC分类号： H01L23/5252 ,  G11C17/18 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： Antifuses and program circuits having the same. The antifuses are embodied as a transistor. When a first power supply voltage is applied to a source, a first program voltage for causing impact ionization is applied to a gate and drain, and a second program voltage for causing channel initiated secondary electron/channel initiated secondary hole (CHISEL/CHISHL) is applied to a well, a dielectric material may be ruptured between the gate adjacent to the drain and the well so that an antifuse may be programmed.

摘要翻译： 防潮和程序电路具有相同的功能。 反熔丝体现为晶体管。 当向源极施加第一电源电压时，将用于引起冲击电离的第一编程电压施加到栅极和漏极，并且用于引起通道引发的次级电子/通道引发的次级孔（CHISEL / CHISHL）的第二编程电压为 应用于阱，电介质材料可能在与漏极和阱之间相邻的栅极之间破裂，从而可以对反熔丝进行编程。

公开(公告)号：US20110221001A1

公开(公告)日：2011-09-15

申请号：US13067239

申请日：2011-05-18

申请人： Ki-Whan Song ,  Nam-Kyun Tak

发明人： Ki-Whan Song ,  Nam-Kyun Tak

IPC分类号： H01L29/78

CPC分类号： H01L27/108 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L29/7841

摘要： Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation.

公开(公告)号：US07851859B2

公开(公告)日：2010-12-14

申请号：US11829113

申请日：2007-07-27

申请人： Nam-Kyun Tak ,  Ki-Whan Song ,  Chang-Woo Oh ,  Woo-Yeong Cho

发明人： Nam-Kyun Tak ,  Ki-Whan Song ,  Chang-Woo Oh ,  Woo-Yeong Cho

IPC分类号： H01L23/62

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/7834 ,  H01L29/7841

摘要： A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.

摘要翻译： 单晶体管浮体动态随机存取存储器（DRAM）器件包括位于半导体衬底上的浮体和位于浮体上的栅电极，浮体包括过剩的载流子存储区。 DRAM器件还包括分别位于栅极两侧的源极和漏极区域以及位于浮体与源极和漏极区域之间的泄漏屏蔽图案。 源极和漏极区域中的每一个接触可以位于源极和漏极区域之间的浮体。 浮体还可以横向延伸在泄漏屏蔽图案下方，这可以布置在栅电极的外侧。

公开(公告)号：US20100149898A1

公开(公告)日：2010-06-17

申请号：US12654282

申请日：2009-12-16

申请人： Nam-Kyun Tak ,  Ki-Whan Song

发明人： Nam-Kyun Tak ,  Ki-Whan Song

IPC分类号： G11C17/16 ,  H01L29/78 ,  G11C5/14

CPC分类号： H01L23/5252 ,  G11C17/18 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： Antifuses and program circuits having the same. The antifuses are embodied as a transistor. When a first power supply voltage is applied to a source, a first program voltage for causing impact ionization is applied to a gate and drain, and a second program voltage for causing channel initiated secondary electron/channel initiated secondary hole (CHISEL/CHISHL) is applied to a well, a dielectric material may be ruptured between the gate adjacent to the drain and the well so that an antifuse may be programmed.

摘要翻译： 防潮和程序电路具有相同的功能。 反熔丝体现为晶体管。 当向源极施加第一电源电压时，将用于引起冲击电离的第一编程电压施加到栅极和漏极，并且用于引起通道引发的次级电子/通道引发的次级孔（CHISEL / CHISHL）的第二编程电压为 应用于阱，电介质材料可能在与漏极和阱之间相邻的栅极之间破裂，从而可以对反熔丝进行编程。

公开(公告)号：US08054693B2

公开(公告)日：2011-11-08

申请号：US12654283

申请日：2009-12-16

申请人： Ki-Whan Song ,  Nam-Kyun Tak

发明人： Ki-Whan Song ,  Nam-Kyun Tak

IPC分类号： G11C16/04

CPC分类号： G11C11/404 ,  G11C11/4076 ,  G11C2211/4016

摘要： In example embodiments, the semiconductor memory device, and the method for operating the semiconductor memory device, includes a memory cell array having a plurality of memory cells each formed of a transistor having a floating body. The transistors are coupled between a plurality of word lines, a plurality of source lines and a plurality of bit lines. Additionally, the memory cell array includes a controller configured to read data from at least one of the memory cells and restore data to the memory cell storing a first data state through a bit operation of the memory cell. The controller restores data to the memory cell by applying a first source-line control voltage to a selected source line and applying a first word-line control voltage to a selected word line in a first period of a read operation. Also, the controller is configured to restore data to the memory cell, which is storing a second data state, by applying a second source-line control voltage to the selected source line and applying a second word-line control voltage to the selected word line in a second period of the read operation.

摘要翻译： 在示例实施例中，半导体存储器件以及用于操作半导体存储器件的方法包括具有多个存储单元的存储单元阵列，每个存储单元均由具有浮体的晶体管形成。 晶体管耦合在多个字线，多条源极线和多个位线之间。 此外，存储单元阵列包括控制器，其被配置为从存储器单元中的至少一个读取数据，并且通过存储器单元的位操作将数据恢复到存储第一数据状态的存储单元。 控制器通过对所选择的源极线施加第一源极线控制电压并且在读取操作的第一周期中对所选择的字线施加第一字线控制电压来将数据恢复到存储器单元。 此外，控制器被配置为通过对所选择的源极线施加第二源极线控制电压并将第二字线控制电压施加到所选择的字线来将数据恢复到存储第二数据状态的存储器单元 在读操作的第二周期。

公开(公告)号：US20110042746A1

公开(公告)日：2011-02-24

申请号：US12940304

申请日：2010-11-05

申请人： Nam-Kyun Tak ,  Ki-Whan Song ,  Chang-Woo Oh ,  Woo-Yeong Cho

发明人： Nam-Kyun Tak ,  Ki-Whan Song ,  Chang-Woo Oh ,  Woo-Yeong Cho

IPC分类号： H01L29/772

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/7834 ,  H01L29/7841

摘要： A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.

摘要翻译： 单晶体管浮体动态随机存取存储器（DRAM）器件包括位于半导体衬底上的浮体和位于浮体上的栅电极，浮体包括过剩的载流子存储区。 DRAM器件还包括分别位于栅极两侧的源极和漏极区域以及位于浮体与源极和漏极区域之间的泄漏屏蔽图案。 源极和漏极区域中的每一个接触可以位于源极和漏极区域之间的浮体。 浮体还可以横向延伸在泄漏屏蔽图案下方，这可以布置在栅电极的外侧。

公开(公告)号：US20090278194A1

公开(公告)日：2009-11-12

申请号：US12453036

申请日：2009-04-28

申请人： Nam-Kyun Tak ,  Ki-Whan Song

发明人： Nam-Kyun Tak ,  Ki-Whan Song

IPC分类号： H01L29/792 ,  H01L29/786

CPC分类号： H01L29/7841 ,  H01L29/785

摘要： A capacitorless one transistor (1T) semiconductor device whose data storage abilities are increased and leakage current is reduced is provided. The capacitor-less 1T semiconductor device includes a buried insulating layer formed on a substrate, an active region formed on the buried insulating layer and including a source region, a drain region and a floating body formed between the source region and the drain region, and a gate pattern formed on the floating body, wherein the floating body includes a main floating body having the same top surface height as one of the source region and the drain region, and a first upper floating body formed between the main floating body and the gate pattern.

摘要翻译： 提供其数据存储能力增加并且漏电流减小的无电容器一晶体管（1T）半导体器件。 电容器1T半导体器件包括形成在基板上的掩埋绝缘层，形成在掩埋绝缘层上的有源区，并且包括源区域，漏极区域和形成在源极区域与漏极区域之间的浮体，以及 形成在所述浮体上的栅极图案，其中所述浮体包括具有与所述源极区域和所述漏极区域中的一个相同的顶部高度的主浮动体，以及形成在所述主浮体和所述栅极之间的第一上浮体 模式。

公开(公告)号：US20090022003A1

公开(公告)日：2009-01-22

申请号：US12171406

申请日：2008-07-11

申请人： Ki-Whan SONG ,  Nam-Kyun Tak

发明人： Ki-Whan SONG ,  Nam-Kyun Tak

IPC分类号： G11C7/00 ,  H01L27/108

CPC分类号： H01L27/108 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L29/7841

摘要： Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation.

摘要翻译： 示例性实施例涉及使用双极结型晶体管（BJT）操作的存储器单元结构，存储器阵列，存储器件，存储器控制器和存储器系统。

公开(公告)号：US20070153664A1

公开(公告)日：2007-07-05

申请号：US11646645

申请日：2006-12-28

申请人： Nam-kyun Tak ,  Chang-hyun Kim ,  Yeong-taek Lee ,  Jae-woong Hyun

发明人： Nam-kyun Tak ,  Chang-hyun Kim ,  Yeong-taek Lee ,  Jae-woong Hyun

IPC分类号： G11B7/135

CPC分类号： G11B7/24088 ,  G11B7/1384 ,  G11B7/24

摘要： There is provided a method and device for reading, writing, or both, data from or to a pattern recognition type optical memory having a light transmittable substrate. Patterns can be formed in the pattern recognition type optical memory from light images representing the data. An optical memory reading device comprises a light source, an image detecting unit for detecting images corresponding to the patterns and generating image signals converted by an optical/electric converter into electric signals. An optical memory writing device comprises a light source, an electric/optical converter for receiving an electric signal corresponding to the data and converting the electric signal into an image signal, and an image generation unit for receiving the light emitted from the light source and the image signal and generating light images corresponding to the image signal, wherein the images are configured to form the patterns on the light transmittable substrate.

摘要翻译： 提供了一种用于从具有可透光衬底的图案识别型光学存储器读取或写入数据的方法和装置。 可以从表示数据的光图像在图案识别型光学存储器中形成图案。 光学存储器读取装置包括光源，用于检测与图案对应的图像的图像检测单元，并且将由光/电转换器转换的图像信号生成为电信号。 一种光学存储器写入装置，包括光源，用于接收对应于数据的电信号并将电信号转换成图像信号的电/光转换器，以及用于接收从光源发射的光和 图像信号并产生对应于图像信号的光图像，其中图像被配置为在可透光基板上形成图案。

公开(公告)号：US08772872B2

公开(公告)日：2014-07-08

申请号：US12588276

申请日：2009-10-09

申请人： Nam-Kyun Tak ,  Ki-Whan Song

发明人： Nam-Kyun Tak ,  Ki-Whan Song

IPC分类号： H01L27/12

CPC分类号： H01L29/7841 ,  H01L21/28114 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/66553 ,  H01L29/7843 ,  H01L29/7846

摘要： Transistors, semiconductor memory cells having a transistor and methods of forming the same are provided, the transistors may include a semiconductor substrate having a first semiconductor region. A gate pattern may be disposed on the first semiconductor region. Spacer patterns may each be disposed on a sidewall of the gate pattern. Second semiconductor regions and a third semiconductor regions may be disposed in the semiconductor substrate. The second semiconductor regions may be disposed under the spacer patterns. The third semiconductor regions may be disposed adjacent to the second semiconductor regions. The first semiconductor region may have a higher impurity ion concentration than the second semiconductor regions.

摘要翻译： 提供了具有晶体管的晶体管，具有晶体管的半导体存储单元及其形成方法，晶体管可以包括具有第一半导体区域的半导体衬底。 栅极图案可以设置在第一半导体区域上。 间隔图案可以各自设置在栅极图案的侧壁上。 第二半导体区域和第三半导体区域可以设置在半导体衬底中。 第二半导体区域可以设置在间隔图案下方。 第三半导体区域可以被布置成与第二半导体区域相邻。 第一半导体区域可以具有比第二半导体区域更高的杂质离子浓度。