利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

114 条记录 (耗时 0.034 秒)

    SINGLE TRANSISTOR MEMORY DEVICE HAVING SOURCE AND DRAIN INSULATING REGIONS AND METHOD OF FABRICATING THE SAME
    1.
    发明申请
    SINGLE TRANSISTOR MEMORY DEVICE HAVING SOURCE AND DRAIN INSULATING REGIONS AND METHOD OF FABRICATING THE SAME 审中-公开
    具有源极和漏极绝缘区域的单晶体管存储器件及其制造方法

    公开(公告)号：US20110042746A1

    公开(公告)日：2011-02-24

    申请号：US12940304

    申请日：2010-11-05

    申请人： Nam-Kyun Tak ,  Ki-Whan Song ,  Chang-Woo Oh ,  Woo-Yeong Cho

    发明人： Nam-Kyun Tak ,  Ki-Whan Song ,  Chang-Woo Oh ,  Woo-Yeong Cho

    IPC分类号： H01L29/772

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/7834 ,  H01L29/7841

    摘要： A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.

    摘要翻译： 单晶体管浮体动态随机存取存储器（DRAM）器件包括位于半导体衬底上的浮体和位于浮体上的栅电极，浮体包括过剩的载流子存储区。 DRAM器件还包括分别位于栅极两侧的源极和漏极区域以及位于浮体与源极和漏极区域之间的泄漏屏蔽图案。 源极和漏极区域中的每一个接触可以位于源极和漏极区域之间的浮体。 浮体还可以横向延伸在泄漏屏蔽图案下方，这可以布置在栅电极的外侧。

    Single transistor memory device having source and drain insulating regions and method of fabricating the same
    2.
    发明授权
    Single transistor memory device having source and drain insulating regions and method of fabricating the same 有权
    具有源极和漏极绝缘区域的单晶体管存储器件及其制造方法

    公开(公告)号：US07851859B2

    公开(公告)日：2010-12-14

    申请号：US11829113

    申请日：2007-07-27

    申请人： Nam-Kyun Tak ,  Ki-Whan Song ,  Chang-Woo Oh ,  Woo-Yeong Cho

    发明人： Nam-Kyun Tak ,  Ki-Whan Song ,  Chang-Woo Oh ,  Woo-Yeong Cho

    IPC分类号： H01L23/62

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/7834 ,  H01L29/7841

    摘要： A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode.

    摘要翻译： 单晶体管浮体动态随机存取存储器（DRAM）器件包括位于半导体衬底上的浮体和位于浮体上的栅电极，浮体包括过剩的载流子存储区。 DRAM器件还包括分别位于栅极两侧的源极和漏极区域以及位于浮体与源极和漏极区域之间的泄漏屏蔽图案。 源极和漏极区域中的每一个接触可以位于源极和漏极区域之间的浮体。 浮体还可以横向延伸在泄漏屏蔽图案下方，这可以布置在栅电极的外侧。

    Phase change memory device generating program current and method thereof
    3.
    发明授权
    Phase change memory device generating program current and method thereof 有权
    相变存储器件产生程序电流及其方法

    公开(公告)号：US08259511B2

    公开(公告)日：2012-09-04

    申请号：US13064672

    申请日：2011-04-07

    申请人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

    发明人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

    IPC分类号： G11C7/10

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

    摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

    摘要翻译： 相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。 存储单元阵列可以包括多个存储单元。 写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。 写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。 控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

    Apparatus and Systems Using Phase Change Memories
    5.
    发明申请
    Apparatus and Systems Using Phase Change Memories 有权
    使用相变记忆的装置和系统

    公开(公告)号：US20110242886A1

    公开(公告)日：2011-10-06

    申请号：US13091238

    申请日：2011-04-21

    申请人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

    发明人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

    IPC分类号： G11C11/21

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092

    摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.

    摘要翻译： 提供了使用相变存储器件的装置和系统。 相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。 每个顺序复位脉冲被输出到多个复位线中相应的一个。 多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。

    Resistance random access memory having common source line
    6.
    发明授权
    Resistance random access memory having common source line 有权
    具有共同源极线的电阻随机存取存储器

    公开(公告)号：US07903448B2

    公开(公告)日：2011-03-08

    申请号：US11964142

    申请日：2007-12-26

    申请人： Hyung-Rok Oh ,  Sang-Beom Kang ,  Joon-Min Park ,  Woo-Yeong Cho

    发明人： Hyung-Rok Oh ,  Sang-Beom Kang ,  Joon-Min Park ,  Woo-Yeong Cho

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/79

    摘要： A resistance random access memory (RRAM) having a source line shared structure and an associated data access method. The RRAM, in which a write operation of writing data of first state and second state to a selected memory cell is performed through first and second write paths having mutually opposite directions, includes word lines, bit lines, a memory cell array and a plurality of source lines. The memory cell array includes a plurality of memory cells each constructed of an access transistor coupled to a resistive memory device. The memory cells are disposed in a matrix of rows and columns and located at each intersection of a word line and a bit line. Each of the plurality of source lines is disposed between a pair of word lines and in the same direction as the word lines. A positive voltage is applied to a source line in a memory cell write operation. Through the source line shared structure, occupied chip area is reduced and, in a write operating mode, a bit line potential can be determined within a positive voltage level range.

    摘要翻译： 具有源线共享结构的电阻随机存取存储器（RRAM）和相关联的数据存取方法。 其中通过具有相互相反方向的第一和第二写入路径来执行将第一状态和第二状态的数据写入所选存储单元的写入操作，包括字线，位线，存储单元阵列和多个 源线。 存储单元阵列包括多个存储单元，每个存储单元由耦合到电阻存储器件的存取晶体管构成。 存储单元被布置成行和列的矩阵并且位于字线和位线的每个交叉点处。 多个源极线中的每一个被设置在一对字线之间并且在与字线相同的方向上。 在存储单元写入操作中，将正电压施加到源极线。 通过源极线共享结构，占用的芯片面积减小，并且在写入操作模式中，可以在正电压电平范围内确定位线电位。

    Phase change memory devices and systems, and related programming methods
    8.
    发明授权
    Phase change memory devices and systems, and related programming methods 有权
    相变存储器件和系统以及相关编程方法

    公开(公告)号：US07529124B2

    公开(公告)日：2009-05-05

    申请号：US11727711

    申请日：2007-03-28

    申请人： Woo-Yeong Cho ,  Kwang-Jin Lee ,  Hye-Jin Kim

    发明人： Woo-Yeong Cho ,  Kwang-Jin Lee ,  Hye-Jin Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078

    摘要： A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.

    摘要翻译： 相变存储器件通过接收在所选择的存储器单元中被编程的程序数据来执行编程操作，当检验读取电压为检测电压时，通过检测流过选择的存储器单元的检验电流的大小来感测已经存储在所选存储单元中的读取数据 应用于所选择的存储单元，确定读取的数据是否与程序数据相同，并且在确定所选择的存储单元中的一个或多个的程序数据与相应的读取数据不相同时，编程所选择的一个或多个 存储单元与程序数据。

    Phase change memory device using multiprogramming method
    9.
    发明授权
    Phase change memory device using multiprogramming method 有权
    相变存储器件采用多重编程方式

    公开(公告)号：US07463511B2

    公开(公告)日：2008-12-09

    申请号：US11723361

    申请日：2007-03-19

    申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

    发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/72

    摘要： A phase change memory device includes a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array includes a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit includes a plurality of write driver units each comprising a plurality of write drivers adapted to provide respective programming currents to a corresponding block unit among the plurality of block units. The column selection circuit is connected between the memory cell array and the write driver circuit and is adapted to select at least one of the plurality of memory blocks in response to a column selection signal to provide corresponding programming currents to the at least one of the plurality of memory blocks.

    摘要翻译： 相变存储器件包括存储单元阵列和写入驱动器电路以及列选择电路。 存储单元阵列包括多个块单元，每个块单元连接在相应的一对字线驱动器之间。 写驱动器电路包括多个写驱动器单元，每个写驱动器单元包括多个写驱动器，其适于向多个块单元中的相应块单元提供相应的编程电流。 列选择电路连接在存储单元阵列和写驱动器电路之间，并且适于响应于列选择信号选择多个存储器块中的至少一个，以向多个存储单元阵列中的至少一个提供对应的编程电流 的内存块。

    Phase-changeable memory device and read method thereof
    10.
    发明授权
    Phase-changeable memory device and read method thereof 有权
    相变存储器件及其读取方法

    公开(公告)号：US07391644B2

    公开(公告)日：2008-06-24

    申请号：US11605212

    申请日：2006-11-29

    申请人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    发明人： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

    摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.

    摘要翻译： 公开了一种可变相存储器件和读取数据的相关方法。 存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。 每个存储单元包括相位可变材料和连接到位线的二极管。 高压电路从电源提供高电压。 预充电电路将位线充电至电源电压后，将位线升高至高电压。 偏置电路通过高电压向位线提供读取电流。 读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。 存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。