公开(公告)号：US20110244640A1

公开(公告)日：2011-10-06

申请号：US13047758

申请日：2011-03-14

Applicant: Yung-Chang Lin ,  Nan-Ray Wu ,  Le-Tien Jung

Inventor： Yung-Chang Lin ,  Nan-Ray Wu ,  Le-Tien Jung

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/76

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/1157 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7881

Abstract: A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.

Abstract translation: 制造闪速存储单元的方法包括提供其上形成有第一介电层的基板，在第一介电层上形成控制栅极，在控制栅极的侧壁上形成氧化物 - 氧化物（ONO）间隔物，形成 在ONO间隔物两侧的衬底上的第二电介质层，并分别在第二电介质层上的ONO间隔物的外侧形成浮栅。

公开(公告)号：US08664062B2

公开(公告)日：2014-03-04

申请号：US13047758

申请日：2011-03-14

Applicant: Yung-Chang Lin ,  Nan-Ray Wu ,  Le-Tien Jung

Inventor： Yung-Chang Lin ,  Nan-Ray Wu ,  Le-Tien Jung

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/76

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/1157 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7881

Abstract: A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.

Abstract translation: 制造闪速存储单元的方法包括提供其上形成有第一介电层的基板，在第一介电层上形成控制栅极，在控制栅极的侧壁上形成氧化物 - 氧化物（ONO）间隔物，形成 在ONO间隔物两侧的衬底上的第二电介质层，并分别在第二电介质层上的ONO间隔物的外侧形成浮栅。

公开(公告)号：US20050157563A1

公开(公告)日：2005-07-21

申请号：US10927391

申请日：2004-08-26

Applicant: Jang-Min Lin ,  Nan-Ray Wu

Inventor： Jang-Min Lin ,  Nan-Ray Wu

IPC: G06F9/445 ,  G11C5/00 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G06F9/4401 ,  G11C11/406

Abstract: A memory device for a mobile communication device. The device includes a pseudo static random access memory (PSRAM), a NAND flash memory, an interface controller and a NOR flash memory. When the mobile communication device is powered on, the microprocessor downloads a system program to the PSRAM from the NAND flash memory and shows a startup icon on a display unit according to an initial program, executing the downloaded system program in the PSRAM to accomplish startup of the mobile communication device.

Abstract translation: 一种用于移动通信设备的存储设备。 该装置包括伪静态随机存取存储器（PSRAM），NAND闪存，接口控制器和NOR闪存。 当移动通信设备通电时，微处理器从NAND闪速存储器将系统程序下载到PSRAM，并根据初始程序在显示单元上显示启动图标，在PSRAM中执行下载的系统程序以完成启动 移动通信设备。