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    Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment
    1.
    发明授权
    Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment 有权
    半导体集成电路，标准单元，标准单元库，半导体集成电路设计方法和半导体集成电路设计设备

    公开(公告)号：US08261225B2

    公开(公告)日：2012-09-04

    申请号：US12714819

    申请日：2010-03-01

    申请人： Tetsurou Toubou ,  Nana Okamoto ,  Junichi Yano

    发明人： Tetsurou Toubou ,  Nana Okamoto ,  Junichi Yano

    IPC分类号： G06F17/50

    CPC分类号： H01L27/11807 ,  G06F17/5072 ,  H01L27/0207

    摘要： A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.

    摘要翻译： 半导体集成电路包括：第一晶体管，其由沿第一方向延伸的第一栅极和第一扩散区域形成，并且能够有效;第二晶体管，由沿第一方向延伸的第二栅极和 第二扩散区，并且在与第一方向成直角相交的第二方向上与第一晶体管相邻布置;以及第三栅极，其在第一方向上延伸并且在第二方向上相对于第一晶体管设置在第一方向上 与第二晶体管相反。 第一栅极和第二栅极之间的空间大于第一栅极和第三栅极之间的空间。

    Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment
    2.
    发明授权
    Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment 有权
    半导体集成电路，标准单元，标准单元库，半导体集成电路设计方法和半导体集成电路设计设备

    公开(公告)号：US07685551B2

    公开(公告)日：2010-03-23

    申请号：US11476124

    申请日：2006-06-28

    申请人： Tetsurou Toubou ,  Nana Okamoto ,  Junichi Yano

    发明人： Tetsurou Toubou ,  Nana Okamoto ,  Junichi Yano

    IPC分类号： G06F17/50

    CPC分类号： H01L27/11807 ,  G06F17/5072 ,  H01L27/0207

    摘要： A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.

    摘要翻译： 半导体集成电路包括：第一晶体管，其由沿第一方向延伸的第一栅极和第一扩散区域形成，并且能够有效;第二晶体管，由沿第一方向延伸的第二栅极和 第二扩散区，并且在与第一方向成直角相交的第二方向上与第一晶体管相邻布置;以及第三栅极，其在第一方向上延伸并且在第二方向上相对于第一晶体管设置在第一方向上 与第二晶体管相反。 第一栅极和第二栅极之间的空间大于第一栅极和第三栅极之间的空间。

    SEMICONDUCTOR INTEGRATED CIRCUIT, STANDARD CELL, STANDARD CELL LIBRARY, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING EQUIPMENT
    3.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT, STANDARD CELL, STANDARD CELL LIBRARY, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING EQUIPMENT 有权
    半导体集成电路，标准电池，标准电池库，半导体集成电路设计方法和半导体集成电路设计设备

    公开(公告)号：US20100148235A1

    公开(公告)日：2010-06-17

    申请号：US12714819

    申请日：2010-03-01

    申请人： Tetsurou Toubou ,  Nana Okamoto ,  Junichi Yano

    发明人： Tetsurou Toubou ,  Nana Okamoto ,  Junichi Yano

    IPC分类号： H01L27/092 ,  H01L27/105

    CPC分类号： H01L27/11807 ,  G06F17/5072 ,  H01L27/0207

    摘要： A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.

    摘要翻译： 半导体集成电路包括：第一晶体管，其由沿第一方向延伸的第一栅极和第一扩散区域形成，并且能够有效;第二晶体管，由沿第一方向延伸的第二栅极和 第二扩散区，并且在与第一方向成直角相交的第二方向上与第一晶体管相邻布置;以及第三栅极，其在第一方向上延伸并且在第二方向上相对于第一晶体管设置在第一方向上 与第二晶体管相反。 第一栅极和第二栅极之间的空间大于第一栅极和第三栅极之间的空间。

    Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit
    4.
    发明授权
    Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit 有权
    标准单元的布局结构，标准单元库和半导体集成电路的布局结构

    公开(公告)号：US08766322B2

    公开(公告)日：2014-07-01

    申请号：US12905873

    申请日：2010-10-15

    申请人： Nana Okamoto ,  Masaki Tamaru ,  Hidetoshi Nishimura

    发明人： Nana Okamoto ,  Masaki Tamaru ,  Hidetoshi Nishimura

    IPC分类号： H01L27/118 ,  H01L27/02

    CPC分类号： H01L23/49827 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.

    摘要翻译： 在不需要电路的逻辑运算的包括截止晶体管126,127的标准单元的布局结构中，虚设通孔触点116,117分别设置在截止晶体管126,127的杂质扩散区域103,106上。 虚拟金属互连122,123分别经由触点116,117连接到虚拟电路。 因此，降低了半导体集成电路的制造成本的原因之一是通孔接点的密度变化减小，从而改善了通孔接点的制造缺陷。

    LAYOUT STRUCTURE OF STANDARD CELL, STANDARD CELL LIBRARY, AND LAYOUT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT
    5.
    发明申请
    LAYOUT STRUCTURE OF STANDARD CELL, STANDARD CELL LIBRARY, AND LAYOUT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    标准单元的布局结构，标准单元库和半导体集成电路的布局结构

    公开(公告)号：US20110031536A1

    公开(公告)日：2011-02-10

    申请号：US12905873

    申请日：2010-10-15

    申请人： Nana Okamoto ,  Masaki Tamaru ,  Hidetoshi Nishimura

    发明人： Nana Okamoto ,  Masaki Tamaru ,  Hidetoshi Nishimura

    IPC分类号： H01L27/118

    CPC分类号： H01L23/49827 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.

    摘要翻译： 在不需要电路的逻辑运算的包括截止晶体管126,127的标准单元的布局结构中，虚设通孔触点116,117分别设置在截止晶体管126,127的杂质扩散区域103,106上。 虚拟金属互连122,123分别经由触点116,117连接到虚拟电路。 因此，降低了半导体集成电路的制造成本的原因之一是通孔接点的密度变化减小，从而改善了通孔接点的制造缺陷。

    Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment
    6.
    发明申请
    Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment 有权
    半导体集成电路，标准单元，标准单元库，半导体集成电路设计方法和半导体集成电路设计设备

    公开(公告)号：US20070004147A1

    公开(公告)日：2007-01-04

    申请号：US11476124

    申请日：2006-06-28

    申请人： Tetsurou Toubou ,  Nana Okamoto ,  Junichi Yano

    发明人： Tetsurou Toubou ,  Nana Okamoto ,  Junichi Yano

    IPC分类号： H01L27/10 ,  H01L21/336

    CPC分类号： H01L27/11807 ,  G06F17/5072 ,  H01L27/0207

    摘要： A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.

    摘要翻译： 半导体集成电路包括：第一晶体管，其由沿第一方向延伸的第一栅极和第一扩散区域形成，并且能够有效;第二晶体管，由沿第一方向延伸的第二栅极和 第二扩散区，并且在与第一方向成直角相交的第二方向上与第一晶体管相邻布置;以及第三栅极，其在第一方向上延伸并且在第二方向上相对于第一晶体管设置在第一方向上 与第二晶体管相反。 第一栅极和第二栅极之间的空间大于第一栅极和第三栅极之间的空间。