公开(公告)号：US06967866B2

公开(公告)日：2005-11-22

申请号：US10800711

申请日：2004-03-16

申请人： Akio Hirata ,  Toshiyuki Moriwaki ,  Tetsurou Toubou ,  Nana Okamoto ,  Mitsuaki Hayashi

发明人： Akio Hirata ,  Toshiyuki Moriwaki ,  Tetsurou Toubou ,  Nana Okamoto ,  Mitsuaki Hayashi

IPC分类号： G11C17/08 ,  G11C11/34 ,  G11C17/00 ,  G11C17/12 ,  H01L21/82 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/112

CPC分类号： G11C17/12

摘要： A dummy MOSFET including a dummy gate separates nMOSFETs included in adjacent memory cells arranged in the direction in which bit lines extend. This configuration reduces a stress applied from an STI to the channel regions of the nMOSFETs. Accordingly, decrease of drive currents of the nMOSFETs is suppressed.

摘要翻译： 包括伪栅极的虚设MOSFET将沿着位线延伸的方向排列的相邻存储单元中包括的nMOSFET分离。 这种配置减小了从STI施加到nMOSFET的沟道区域的应力。 因此，抑制了nMOSFET的驱动电流的降低。

公开(公告)号：US20100156450A1

公开(公告)日：2010-06-24

申请号：US12710992

申请日：2010-02-23

申请人： Hiroshi INADA ,  Akio Hirata

发明人： Hiroshi INADA ,  Akio Hirata

IPC分类号： G01R31/02

CPC分类号： H03K19/00384

摘要： A semiconductor integrated circuit device 100A includes: an integrated circuit body 106A having a plurality of MOSFETs on a semiconductor substrate; a plurality of elements 102A to be measured placed on the same substrate as the plurality of MOSFETs; a monitor circuit 105A for selecting an element to be measured whose measured parameter value is in a predetermined rank among the plurality of elements 102A to be measured as an element 101A to be measured for monitoring; and an operation parameter adjustment circuit 107 for adjusting an operation parameter 108 supplied to the integrated circuit body 106A based on the measured parameter 104A of the element to be measured for monitoring.

摘要翻译： 半导体集成电路器件100A包括：在半导体衬底上具有多个MOSFET的集成电路体106A; 待测量的多个元件102A放置在与多个MOSFET相同的衬底上; 监视电路105A，用于选择要测量的多个要测量的元素102A中的测量参数值为预定等级的待测量元素作为待测量元素101A进行监测; 以及操作参数调整电路107，用于基于要测量的元件的测量参数104A来调整提供给集成电路体106A的操作参数108以进行监视。

公开(公告)号：US20070226671A1

公开(公告)日：2007-09-27

申请号：US11723580

申请日：2007-03-21

申请人： Akio Hirata

发明人： Akio Hirata

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： In a method and apparatus for designing semiconductor integrated circuit, a path delay information producing section produces path delay information by performing a static timing analysis based on delay information of a cell and subject circuit information. A correction table producing section calculates circuit-dependent delay variation for each combination of circuit parameter values based on variation information of an element, and stores the calculated circuit-dependent delay variation in a delay correction table. A statistical path delay producing section calculates the circuit parameters for a path based on the subject circuit information and the path delay information, obtains the corresponding circuit-dependent delay variation based on the circuit-dependent delay variation correction table, and calculates and outputs statistical path delay information based on the circuit-dependent delay variation and the corresponding path delay information. Thus, it is possible to obtain a value close to an actual path delay worst value with only a little addition of calculation time.

摘要翻译： 在用于设计半导体集成电路的方法和装置中，路径延迟信息产生部分通过基于小区和被摄体电路信息的延迟信息执行静态时序分析来产生路径延迟信息。 校正表生成部根据元件的变化信息对电路参数值的各组合计算电路相关的延迟变化，并将所计算的电路相关延迟变化存储在延迟校正表中。 统计路径延迟产生部分基于目标电路信息和路径延迟信息计算路径的电路参数，基于电路相关延迟变化校正表获得相应的电路相关延迟变化，并计算并输出统计路径 延迟信息基于电路相关的延迟变化和相应的路径延迟信息。 因此，只需稍微增加计算时间即可获得接近实际路径延迟最差值的值。

公开(公告)号：US06853228B2

公开(公告)日：2005-02-08

申请号：US10686597

申请日：2003-10-17

申请人： Akio Hirata ,  Masahiro Gion ,  Kazuyuki Nakanishi

发明人： Akio Hirata ,  Masahiro Gion ,  Kazuyuki Nakanishi

IPC分类号： H03K3/012 ,  H03K3/037

CPC分类号： H03K3/012 ,  H03K3/037

摘要： In a flip-flop circuit which includes an input section using a dynamic circuit and an output section using a static circuit and which captures data during a period of a pulse width shorter than a clock cycle, the number of transistors, circuit area and power consumption are reduced. In FIG. 1, an output signal of an inverter circuit INV1 constituting a latch circuit 2 connected to the output terminal of an input section 1 is used as an input signal of a control section 3. Thus, a control signal output from the control section 3 to the input section 1 is stabilized, thereby suppressing unnecessary operation of circuit elements and reducing unnecessary power consumption. In addition, the configuration of the control section 3 is simplified. As a result, the number of transistors constituting the circuit and the circuit area can be reduced.

摘要翻译： 在包括使用动态电路的输入部分和使用静态电路的输出部分并且在短于时钟周期的脉冲宽度的周期内捕获数据的触发器电路中，晶体管数量，电路面积和功率消耗 减少了 在图 如图1所示，构成与输入部1的输出端子连接的锁存电路2的反相器电路INV1的输出信号被用作控制部分3的输入信号。因此，从控制部分3输出到控制部分3的控制信号 输入部分1稳定，从而抑制电路元件的不必要的操作并减少不必要的功耗。 另外，简化了控制部3的结构。 结果，可以减少构成电路的晶体管的数量和电路面积。

公开(公告)号：US06229722B1

公开(公告)日：2001-05-08

申请号：US09456317

申请日：1999-12-08

申请人： Kosaku Ichikawa ,  Akio Hirata ,  Kazuto Kawakami ,  Kazuhiro Satoh

发明人： Kosaku Ichikawa ,  Akio Hirata ,  Kazuto Kawakami ,  Kazuhiro Satoh

IPC分类号： H02M700

CPC分类号： H02M7/49 ,  H02M7/10 ,  H02M7/5395 ,  H02M2001/325

摘要： A multiple inverter system of the present invention is disclosed. It includes a plurality of input transformers having secondary windings and a plurality of unit inverter cells connected in series at n stages to compose respective phases and supply the electric power to a multiple phase load in combination with the input transformers. The input transformers have 3n sets of three-phase windings at the secondary side and the secondary windings of the transformers, which are out-of-phase at each phase, are connected to unit inverter cells of each phase at the n-th stages. Further, the present invention is provided with a bypass switch control to melt a fuse that is applicable to a unit inverter given with a circuit closing command by giving this circuit closing command to a bypass switch corresponding to applicable unit inverters in response to an operation abnormality detector and a DC abnormality detector.

摘要翻译： 公开了本发明的多逆变器系统。 它包括具有次级绕组的多个输入变压器和以n个级串联连接的多个单位反相器单元，以组成各个相，并将电力与输入变压器相结合地提供给多相负载。 输入变压器在次级侧具有3n组三相绕组，并且在每相处于异相的变压器的次级绕组在第n级连接到各相的单元逆变器单元。 此外，本发明提供了一种旁路开关控制，用于熔化适用于具有电路关闭命令的单元逆变器的保险丝，该电路关闭命令响应于操作异常向与可应用单元逆变器相对应的旁路开关给予该闭路指令 检测器和直流异常检测器。

公开(公告)号：US4441148A

公开(公告)日：1984-04-03

申请号：US347168

申请日：1982-02-09

申请人： Akio Hirata

发明人： Akio Hirata

IPC分类号： H02H7/12 ,  H02H7/122 ,  H02M1/00 ,  H02H7/125

CPC分类号： H02H7/1225 ,  H02H7/12

摘要： A power converting device including at least one power converting element, and a protection circuit monitoring the switching characteristics of the power converting element and for protecting the power converting element during switching thereof, including a first circuit coupled to detect a reverse voltage applied to the power converting element, a second circuit coupled to the first circuit for receiving the detected reverse voltage and for integrating the detected reverse voltage to produce a reverse voltage/time integral signal, and a third circuit coupled to receive the reverse voltage/time integral signal for producing a decision signal only when the amplitude of the reverse voltage/time integral signal exceeds a first prescribed value, the decision signal indicates that the power converting element is extinguished.

摘要翻译： 一种功率转换装置，包括至少一个功率转换元件，以及保护电路，其监测功率转换元件的开关特性并用于在开关期间保护功率转换元件，包括耦合以检测施加到功率的反向电压的第一电路 转换元件，耦合到第一电路的第二电路，用于接收所检测的反向电压，并用于积分所检测的反向电压以产生反向电压/时间积分信号;以及第三电路，耦合以接收反向电压/时间积分信号以产生 判定信号仅在反向电压/时间积分信号的振幅超过第一规定值时，判定信号表示电力转换元件熄灭。

公开(公告)号：US20140044683A1

公开(公告)日：2014-02-13

申请号：US14022983

申请日：2013-09-10

申请人： Masafumi Kitakaze ,  Tetsuo Minamino ,  Akio Hirata

发明人： Masafumi Kitakaze ,  Tetsuo Minamino ,  Akio Hirata

IPC分类号： A61K35/12 ,  A61K31/7076

CPC分类号： A61K35/34 ,  A61K9/0019 ,  A61K9/19 ,  A61K31/7076 ,  A61K35/12 ,  A61K35/28 ,  A61L27/3804 ,  A61L27/3839 ,  A61L27/3895 ,  A61K2300/00

摘要： The present invention provides a regeneration promoter for regenerating tissue with the use of somatic stem cells. The invention also provides a cell fusion promoter comprising ATP or its metabolite which is safely usable in vivo, a method of producing fused cells in the presence of ATP or its metabolite and a related pharmaceutical composition for regenerating or improving the function of a tissue or an organ in a subject suffering from dysfunction or hypofunction due to injury or denaturation.

摘要翻译： 本发明提供了使用体细胞干细胞再生组织的再生促进剂。 本发明还提供了包含可在体内安全使用的ATP或其代谢物的细胞融合启动子，在ATP或其代谢物存在下产生融合细胞的方法和用于再生或改善组织或功能的功能的相关药物组合物 患有由于损伤或变性引起的功能障碍或功能衰竭的受试者的器官。

公开(公告)号：US07336116B2

公开(公告)日：2008-02-26

申请号：US11342568

申请日：2006-01-31

申请人： Akio Hirata ,  Takahiro Ichinomiya ,  Takashi Ando

发明人： Akio Hirata ,  Takahiro Ichinomiya ,  Takashi Ando

IPC分类号： G06F1/04 ,  H03K3/00

CPC分类号： G06F1/10

摘要： The clock supply circuit of the present invention comprises a plurality of clock supply paths and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the branched clock signals to a plurality of sequential circuits via a buffer. The clock gate circuit is inserted at least to one of the clock supply paths, which lets through the clock signals when a control signal is in a first logic state and, when the control signal is in a second logic state, outputs an inversion signal of a logic level that is outputted in a previous occasion where the control signal in the second logic state is applied.

摘要翻译： 本发明的时钟供给电路包括多个时钟供给路径和时钟门电路。 时钟供应路径分支时钟信号，并且经由缓冲器将每个分支时钟信号提供给多个顺序电路。 时钟门电路至少插入到时钟供给路径中的一个，当控制信号处于第一逻辑状态时，时钟供给路径通过时钟信号，并且当控制信号处于第二逻辑状态时，输出反相信号 在施加第二逻辑状态的控制信号的前一时刻输出的逻辑电平。

公开(公告)号：US20060170479A1

公开(公告)日：2006-08-03

申请号：US11342568

申请日：2006-01-31

申请人： Akio Hirata ,  Takahiro Ichinomiya ,  Takashi Ando

发明人： Akio Hirata ,  Takahiro Ichinomiya ,  Takashi Ando

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： The clock supply circuit of the present invention comprises a plurality of clock supply paths and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the branched clock signals to a plurality of sequential circuits via a buffer. The clock gate circuit is inserted at least to one of the clock supply paths, which lets through the clock signals when a control signal is in a first logic state and, when the control signal is in a second logic state, outputs an inversion signal of a logic level that is outputted in a previous occasion where the control signal in the second logic state is applied.

摘要翻译： 本发明的时钟供给电路包括多个时钟供给路径和时钟门电路。 时钟供应路径分支时钟信号，并且经由缓冲器将每个分支时钟信号提供给多个顺序电路。 时钟门电路至少插入到时钟供给路径中的一个，当控制信号处于第一逻辑状态时，时钟供给路径通过时钟信号，并且当控制信号处于第二逻辑状态时，输出反相信号 在施加第二逻辑状态的控制信号的前一时刻输出的逻辑电平。

公开(公告)号：US4736148A

公开(公告)日：1988-04-05

申请号：US914273

申请日：1986-10-02

申请人： Akio Hirata

发明人： Akio Hirata

IPC分类号： H02M5/45 ,  H02M7/527 ,  H02P27/06 ,  H02P3/18

CPC分类号： H02P27/06 ,  H02M5/4505 ,  H02M7/527 ,  H02P2201/03

摘要： A self-extinguishing element such as a gate turn-off thyristor (GTO) is used for each arm of the inverter. A capacitive load is connected to the output terminal of the inverter. In a region where the output frequency of the inverter is low, the self-extinguishing element is forcibly commutated. In a high-frequency region, where the output frequency of the inverter is higher than that in the low-frequency region, the capacitive load causes the self-extinguishing element to be load-commutated.

摘要翻译： 逆变器的每个臂都使用自熄灭元件，如门极关断晶闸管（GTO）。 电容性负载连接到逆变器的输出端。 在逆变器的输出频率低的区域，强制换向自熄元件。 在逆变器的输出频率高于低频区域的高频区域中，容性负载使得自熄元件被负载换向。