公开(公告)号：US20110286260A1

公开(公告)日：2011-11-24

申请号：US13018757

申请日：2011-02-01

Applicant: Takayuki TSUKAMOTO ,  Yoichi Minemura ,  Natsuki Kikuchi ,  Mitsuru Sato ,  Hiroshi Kanno ,  Takafumi Shimotori

Inventor： Takayuki TSUKAMOTO ,  Yoichi Minemura ,  Natsuki Kikuchi ,  Mitsuru Sato ,  Hiroshi Kanno ,  Takafumi Shimotori

IPC: G11C11/00 ,  H01L45/00

CPC classification number: H01L45/04 ,  G11C5/147 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/72 ,  H01L45/145

Abstract: According to one embodiment, a nonvolatile memory device includes a memory unit and a control unit. The memory unit includes first and second interconnects, and a memory cell. The second interconnect is non-parallel to the first interconnect. The memory cell includes a resistance change layer provided at an intersection between the first and second interconnects. The control unit is connected to the first and second interconnects to supply voltage and current to the resistance change layer. The control unit increases an upper limit of a current supplied to the first interconnect based on a change of a potential of the first interconnect when applying a set operation voltage to the first interconnect in a set operation of changing the resistance change layer from a first state with a first resistance value to a second state with a second resistance value being less than the first resistance value.

Abstract translation: 根据一个实施例，非易失性存储器件包括存储器单元和控制单元。 存储单元包括第一和第二互连以及存储单元。 第二互连与第一互连不平行。 存储单元包括设置在第一和第二互连之间的交叉点处的电阻变化层。 控制单元连接到第一和第二互连以向电阻变化层提供电压和电流。 控制单元在将电阻变化层从第一状态变化的设定动作中，基于第一配线的电位的变化来增大提供给第一配线的电流的上限， 具有第一电阻值到第二状态，其中第二电阻值小于第一电阻值。

公开(公告)号：US20120069627A1

公开(公告)日：2012-03-22

申请号：US13233679

申请日：2011-09-15

Applicant: Yoichi MINEMURA ,  Takayuki TSUKAMOTO ,  Takafumi SHIMOTORI ,  Hiroshi KANNO ,  Natsuki KIKUCHI ,  Mitsuru SATO

Inventor： Yoichi MINEMURA ,  Takayuki TSUKAMOTO ,  Takafumi SHIMOTORI ,  Hiroshi KANNO ,  Natsuki KIKUCHI ,  Mitsuru SATO

IPC: G11C11/00

CPC classification number: G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C29/025 ,  G11C29/028 ,  G11C2013/0083 ,  G11C2213/71

Abstract: A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.

Abstract translation: 非易失性半导体存储器件包括：包括多个第一线，多个第二线和多个存储单元的存储单元阵列，每个存储单元包括可变电阻元件; 第一解码器，连接到所述多条第一线的至少一端，并被配置为选择所述第一线中的至少一条线; 至少一对第二解码器，连接到所述多个第二线路的两端，并且被配置为使得所述一对第二解码器中的一个被选择用于根据所述第一线选择的所述第一线之间的距离来选择所述第二线 解码器和第二行的两端; 以及电压施加电路，被配置为在由第一解码器和第二解码器选择的第一线和第二线之间施加一定电压。

公开(公告)号：US08274822B2

公开(公告)日：2012-09-25

申请号：US13018757

申请日：2011-02-01

Applicant: Takayuki Tsukamoto ,  Yoichi Minemura ,  Natsuki Kikuchi ,  Mitsuru Sato ,  Hiroshi Kanno ,  Takafumi Shimotori

Inventor： Takayuki Tsukamoto ,  Yoichi Minemura ,  Natsuki Kikuchi ,  Mitsuru Sato ,  Hiroshi Kanno ,  Takafumi Shimotori

IPC: G11C11/00

CPC classification number: H01L45/04 ,  G11C5/147 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/72 ,  H01L45/145

Abstract: According to one embodiment, a nonvolatile memory device includes a memory unit and a control unit. The memory unit includes first and second interconnects, and a memory cell. The second interconnect is non-parallel to the first interconnect. The memory cell includes a resistance change layer provided at an intersection between the first and second interconnects. The control unit is connected to the first and second interconnects to supply voltage and current to the resistance change layer. The control unit increases an upper limit of a current supplied to the first interconnect based on a change of a potential of the first interconnect when applying a set operation voltage to the first interconnect in a set operation of changing the resistance change layer from a first state with a first resistance value to a second state with a second resistance value being less than the first resistance value.

Abstract translation: 根据一个实施例，非易失性存储器件包括存储器单元和控制单元。 存储单元包括第一和第二互连以及存储单元。 第二互连与第一互连不平行。 存储单元包括设置在第一和第二互连之间的交叉点处的电阻变化层。 控制单元连接到第一和第二互连以向电阻变化层提供电压和电流。 控制单元在将电阻变化层从第一状态变化的设定动作中，基于第一配线的电位的变化来增大提供给第一配线的电流的上限， 具有第一电阻值到第二状态，其中第二电阻值小于第一电阻值。

公开(公告)号：US08675388B2

公开(公告)日：2014-03-18

申请号：US13233679

申请日：2011-09-15

Applicant: Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Natsuki Kikuchi ,  Mitsuru Sato

Inventor： Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Natsuki Kikuchi ,  Mitsuru Sato

IPC: G11C11/00

CPC classification number: G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C29/025 ,  G11C29/028 ,  G11C2013/0083 ,  G11C2213/71

Abstract: A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.

Abstract translation: 非易失性半导体存储器件包括：包括多个第一线，多个第二线和多个存储单元的存储单元阵列，每个存储单元包括可变电阻元件; 第一解码器，连接到所述多条第一线的至少一端，并被配置为选择所述第一线中的至少一条线; 至少一对第二解码器，连接到所述多个第二线路的两端，并且被配置为使得所述一对第二解码器中的一个被选择用于根据所述第一线选择的所述第一线之间的距离来选择所述第二线 解码器和第二行的两端; 以及电压施加电路，被配置为在由第一解码器和第二解码器选择的第一线和第二线之间施加一定电压。