公开(公告)号：US08605485B2

公开(公告)日：2013-12-10

申请号：US13350067

申请日：2012-01-13

Applicant: Hiroshi Kanno ,  Takafumi Shimotori ,  Yoichi Minemura ,  Takahiko Sasaki ,  Takayuki Tsukamoto

Inventor： Hiroshi Kanno ,  Takafumi Shimotori ,  Yoichi Minemura ,  Takahiko Sasaki ,  Takayuki Tsukamoto

IPC: G11C11/00

CPC classification number: G11C13/0002 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0083

Abstract: According to one embodiment, a control unit multiple-selects a first line for every N lines from a plurality of first lines. N is an integer greater than or equal to one. The control unit sets the multiple-selected first lines to a selection potential, and fixes potentials of non-selected first lines at least adjacent to the multiple-selected first lines at a first timing. The control unit causes the multiple-selected first lines to be in a floating state at a second timing after the first timing. The control unit selects one second line from the plurality of second lines and sets the one second line to a forming potential at a third timing after the second timing.

Abstract translation: 根据一个实施例，控制单元从多条第一行为每N条线选择第一行。 N是大于或等于1的整数。 控制单元将多个选择的第一行设置为选择电位，并且在第一定时将至少与多个选择的第一行相邻的未选择的第一行的电位进行固定。 控制单元使第一定时后的第二定时使多选第一行处于浮动状态。 控制单元从多条第二行中选择一条第二行，并在第二定时之后的第三定时将一条第二行设置成一个形成电位。

公开(公告)号：US20120069627A1

公开(公告)日：2012-03-22

申请号：US13233679

申请日：2011-09-15

Applicant: Yoichi MINEMURA ,  Takayuki TSUKAMOTO ,  Takafumi SHIMOTORI ,  Hiroshi KANNO ,  Natsuki KIKUCHI ,  Mitsuru SATO

Inventor： Yoichi MINEMURA ,  Takayuki TSUKAMOTO ,  Takafumi SHIMOTORI ,  Hiroshi KANNO ,  Natsuki KIKUCHI ,  Mitsuru SATO

IPC: G11C11/00

CPC classification number: G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C29/025 ,  G11C29/028 ,  G11C2013/0083 ,  G11C2213/71

Abstract: A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.

Abstract translation: 非易失性半导体存储器件包括：包括多个第一线，多个第二线和多个存储单元的存储单元阵列，每个存储单元包括可变电阻元件; 第一解码器，连接到所述多条第一线的至少一端，并被配置为选择所述第一线中的至少一条线; 至少一对第二解码器，连接到所述多个第二线路的两端，并且被配置为使得所述一对第二解码器中的一个被选择用于根据所述第一线选择的所述第一线之间的距离来选择所述第二线 解码器和第二行的两端; 以及电压施加电路，被配置为在由第一解码器和第二解码器选择的第一线和第二线之间施加一定电压。

公开(公告)号：US20140063906A1

公开(公告)日：2014-03-06

申请号：US13722210

申请日：2012-12-20

Applicant: Yoichi Minemura ,  Takayuki Tsukamoto ,  Hiroshi Kanno ,  Takamasa Okawa

Inventor： Yoichi Minemura ,  Takayuki Tsukamoto ,  Hiroshi Kanno ,  Takamasa Okawa

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided at each of intersections of a plurality of first lines and a plurality of second lines;and a control circuit applying a selected first line voltage to a selected first line, an adjacent unselected first line voltage which is larger than the selected first line voltage to an adjacent unselected first line, and an unselected first line voltage which is larger than the adjacent unselected first line voltage to an unselected first line, and applying a selected second line voltage which is larger than the selected first line voltage to a selected second line and an unselected second line voltage which is smaller than the selected second line voltage to an unselected second line.

Abstract translation: 根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括设置在多个第一线和多条第二线的每个交点处的多个存储单元; 以及控制电路，将所选择的第一线电压施加到所选择的第一线，相对于相邻未选择的第一线大于所选择的第一线电压的相邻未选择的第一线电压，以及大于相邻的未选择的第一线电压的未选择的第一线电压 将未选择的第一线电压提供给未选择的第一线，以及将选择的第二线电压大于所选择的第一线电压至选定的第二线，以及将小于所选择的第二线电压的未选择的第二线电压施加到未选择的第二线电压 线。

公开(公告)号：US20130229854A1

公开(公告)日：2013-09-05

申请号：US13600448

申请日：2012-08-31

Applicant: Yoichi MINEMURA ,  Takayuki TSUKAMOTO ,  Hiroshi KANNO ,  Takamasa OKAWA

Inventor： Yoichi MINEMURA ,  Takayuki TSUKAMOTO ,  Hiroshi KANNO ,  Takamasa OKAWA

IPC: G11C13/00

CPC classification number: G11C13/0002 ,  G11C11/1673 ,  G11C11/419 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/72

Abstract: A memory cell array includes memory cells disposed at intersections of first lines and second lines, and each having a rectifying element and a variable resistance element connected in series. A control circuit, when performing an operation to change retained data, applies a first voltage to a selected first line and applies a second voltage to a selected second line; furthermore, applies a third voltage to a non-selected first line; and, moreover, applies a fourth voltage larger than the third voltage to a non-selected second line. An absolute value of a difference between the third voltage and the fourth voltage is set smaller than an absolute value of a difference between the first voltage and the second voltage by an amount of an offset voltage. A value of the offset voltage increases as the absolute value of the difference between the first and second voltages increases.

Abstract translation: 存储单元阵列包括设置在第一线和第二线的交点处的存储单元，并且每个具有串联连接的整流元件和可变电阻元件。 控制电路在执行改变保留数据的操作时，将第一电压施加到所选择的第一行，并将第二电压施加到所选择的第二行; 此外，将第三电压施加到未选择的第一线; 此外，将大于第三电压的第四电压施加到未选择的第二线。 将第三电压和第四电压之间的差的绝对值设定为小于第一电压和第二电压之间的差的绝对值除以偏移电压的量。 随着第一和第二电压之间的差的绝对值增加，偏移电压的值增加。

公开(公告)号：US20130229853A1

公开(公告)日：2013-09-05

申请号：US13599301

申请日：2012-08-30

Applicant: Yoichi MINEMURA ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Tomonori Kurosawa ,  Mizuki Kaneko

Inventor： Yoichi MINEMURA ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Tomonori Kurosawa ,  Mizuki Kaneko

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/72

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of cell array blocks and a control circuit. The control circuit sets a selected bit line to have 0 volt, applies a first electric potential which is higher than 0 volt to a selected word line, applies a second electric potential which is higher than 0 volt and lower than the first electric potential to non-selected word lines other than the selected word line, applies a third electric potential which is 0 volt or more and lower than the second electric potential to a non-selected bit line adjacent to the selected bit line in an adjacent cell array block, applies the second electric potential to non-selected bit lines other than the non-selected bit line to which the third electric potential is applied, and changes a resistance status of the resistance variable film of the selected memory cell.

Abstract translation: 根据一个实施例，半导体存储器件包括多个单元阵列块和控制电路。 控制电路将所选择的位线设置为具有0伏特，对所选择的字线施加高于0伏的第一电位，将比第一电位高于0伏且低于第一电位的第二电位施加到非 - 除了所选字线以外的选定字线，将相邻单元阵列块中与选定位线相邻的未选位线施加0伏以上且低于第2电位的第3电位， 对除了施加了第三电位的未选位线之外的非选择位线的第二电位，并且改变所选存储单元的电阻变化膜的电阻状态。

公开(公告)号：US20130229851A1

公开(公告)日：2013-09-05

申请号：US13597814

申请日：2012-08-29

Applicant: Tomonori KUROSAWA ,  Mizuki Kaneko ,  Takafumi Shimotori ,  Takayuki Tsukamoto ,  Yoichi Minemura ,  Hiroshi Kanno

Inventor： Tomonori KUROSAWA ,  Mizuki Kaneko ,  Takafumi Shimotori ,  Takayuki Tsukamoto ,  Yoichi Minemura ,  Hiroshi Kanno

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0083 ,  G11C2213/72

Abstract: In a memory cell array, memory cells each including a variable resistance element are arranged at crossing portions between a plurality of first wiring and a plurality of second wirings. A control circuit executes a set operation, a reset operation, and a training operation. In the set operation, a set pulse is applied to the variable resistance element to change the variable resistance element from a high resistance state to a low resistance state. In the reset operation, a reset pulse having an opposite polarity to the polarity of the set pulse is applied to the variable resistance element to change the variable resistance element from the low resistance state to the high resistance state. In the training operation, the set pulse and the reset pulse are continuously applied to the variable resistance element.

Abstract translation: 在存储单元阵列中，包括可变电阻元件的存储单元布置在多个第一布线和多个第二布线之间的交叉部分处。 控制电路执行设定操作，复位操作和训练操作。 在设定动作中，向可变电阻元件施加设定脉冲，将可变电阻元件从高电阻状态变为低电阻状态。 在复位操作中，将具有与设定脉冲的极性相反的极性的复位脉冲施加到可变电阻元件，以将可变电阻元件从低电阻状态改变为高电阻状态。 在训练操作中，将设定脉冲和复位脉冲连续施加到可变电阻元件。

公开(公告)号：US20120224411A1

公开(公告)日：2012-09-06

申请号：US13350067

申请日：2012-01-13

Applicant: Hiroshi KANNO ,  Takafumi Shimotori ,  Yoichi Minemura ,  Takahiko Sasaki ,  Takayuki Tsukamoto

Inventor： Hiroshi KANNO ,  Takafumi Shimotori ,  Yoichi Minemura ,  Takahiko Sasaki ,  Takayuki Tsukamoto

IPC: G11C11/21

CPC classification number: G11C13/0002 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0083

Abstract: According to one embodiment, a control unit multiple-selects a first line for every N lines from a plurality of first lines. N is an integer greater than or equal to one. The control unit sets the multiple-selected first lines to a selection potential, and fixes potentials of non-selected first lines at least adjacent to the multiple-selected first lines at a first timing. The control unit causes the multiple-selected first lines to be in a floating state at a second timing after the first timing. The control unit selects one second line from the plurality of second lines and sets the one second line to a forming potential at a third timing after the second timing.

Abstract translation: 根据一个实施例，控制单元从多条第一行为每N条线选择第一行。 N是大于或等于1的整数。 控制单元将多个选择的第一行设置为选择电位，并且在第一定时将至少与多个选择的第一行相邻的未选择的第一行的电位进行固定。 控制单元使第一定时后的第二定时使多选第一行处于浮动状态。 控制单元从多条第二行中选择一条第二行，并在第二定时之后的第三定时将一条第二行设置成一个形成电位。

公开(公告)号：US20110286260A1

公开(公告)日：2011-11-24

申请号：US13018757

申请日：2011-02-01

Applicant: Takayuki TSUKAMOTO ,  Yoichi Minemura ,  Natsuki Kikuchi ,  Mitsuru Sato ,  Hiroshi Kanno ,  Takafumi Shimotori

Inventor： Takayuki TSUKAMOTO ,  Yoichi Minemura ,  Natsuki Kikuchi ,  Mitsuru Sato ,  Hiroshi Kanno ,  Takafumi Shimotori

IPC: G11C11/00 ,  H01L45/00

CPC classification number: H01L45/04 ,  G11C5/147 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/72 ,  H01L45/145

Abstract: According to one embodiment, a nonvolatile memory device includes a memory unit and a control unit. The memory unit includes first and second interconnects, and a memory cell. The second interconnect is non-parallel to the first interconnect. The memory cell includes a resistance change layer provided at an intersection between the first and second interconnects. The control unit is connected to the first and second interconnects to supply voltage and current to the resistance change layer. The control unit increases an upper limit of a current supplied to the first interconnect based on a change of a potential of the first interconnect when applying a set operation voltage to the first interconnect in a set operation of changing the resistance change layer from a first state with a first resistance value to a second state with a second resistance value being less than the first resistance value.

Abstract translation: 根据一个实施例，非易失性存储器件包括存储器单元和控制单元。 存储单元包括第一和第二互连以及存储单元。 第二互连与第一互连不平行。 存储单元包括设置在第一和第二互连之间的交叉点处的电阻变化层。 控制单元连接到第一和第二互连以向电阻变化层提供电压和电流。 控制单元在将电阻变化层从第一状态变化的设定动作中，基于第一配线的电位的变化来增大提供给第一配线的电流的上限， 具有第一电阻值到第二状态，其中第二电阻值小于第一电阻值。

公开(公告)号：US20110068373A1

公开(公告)日：2011-03-24

申请号：US12886090

申请日：2010-09-20

Applicant: Yoichi MINEMURA ,  Hiroyuki Nagashima

Inventor： Yoichi MINEMURA ,  Hiroyuki Nagashima

IPC: H01L27/118

CPC classification number: H01L27/2481 ,  H01L27/0688 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147

Abstract: A semiconductor memory device according to an embodiment includes: a cell array block having, above a semiconductor substrate, a plurality of first and second wirings intersecting with one another, and a plurality of memory cells, the first and second wirings being separately formed in a plurality of layers in a perpendicular direction to the semiconductor substrate; and a first via wiring, connecting the first wiring in an n1-th layer of the cell array block with the first wiring in an n2-th layer, the semiconductor substrate or another metal wiring, and extending in a laminating direction of the cell array block. The first via wiring has a cross section orthogonal to the laminating direction of the cell array block. The cross section has an elliptical shape and a longer diameter in a direction perpendicular to the first wiring direction.

Abstract translation: 根据实施例的半导体存储器件包括：单元阵列块，其在半导体衬底上方具有彼此相交的多个第一和第二布线，以及多个存储单元，所述第一和第二布线分别形成在 在与半导体衬底垂直的方向上的多个层; 以及第一通孔布线，将第一电极阵列块的第n1层中的第一布线与第n2层的第一布线，半导体基板或其他金属布线连接，并且在电池阵列的层叠方向上延伸 块。 第一通孔布线具有与单元阵列块的层叠方向正交的截面。 横截面在垂直于第一布线方向的方向上具有椭圆形状和较长直径。

公开(公告)号：US09099180B2

公开(公告)日：2015-08-04

申请号：US13599301

申请日：2012-08-30

Applicant: Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Tomonori Kurosawa ,  Mizuki Kaneko

Inventor： Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Tomonori Kurosawa ,  Mizuki Kaneko

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/72

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of cell array blocks and a control circuit. The control circuit sets a selected bit line to have 0 volt, applies a first electric potential which is higher than 0 volt to a selected word line, applies a second electric potential which is higher than 0 volt and lower than the first electric potential to non-selected word lines other than the selected word line, applies a third electric potential which is 0 volt or more and lower than the second electric potential to a non-selected bit line adjacent to the selected bit line in an adjacent cell array block, applies the second electric potential to non-selected bit lines other than the non-selected bit line to which the third electric potential is applied, and changes a resistance status of the resistance variable film of the selected memory cell.

Abstract translation: 根据一个实施例，半导体存储器件包括多个单元阵列块和控制电路。 控制电路将所选择的位线设置为具有0伏特，对所选择的字线施加高于0伏的第一电位，将比第一电位高于0伏且低于第一电位的第二电位施加到非 - 除了所选字线以外的选定字线，将相邻单元阵列块中与选定位线相邻的未选位线施加0伏以上且低于第2电位的第3电位， 对除了施加了第三电位的未选位线之外的非选择位线的第二电位，并且改变所选存储单元的电阻变化膜的电阻状态。