公开(公告)号：US20140035648A1

公开(公告)日：2014-02-06

申请号：US13563431

申请日：2012-07-31

申请人： Neil E. Birns ,  Craig A. MacKenna

发明人： Neil E. Birns ,  Craig A. MacKenna

IPC分类号： H03K3/00

CPC分类号： G04F1/005 ,  G04F3/06 ,  H03K7/08

摘要： A counter/timer circuit and a method of operating the counter/timer circuit are described. In one embodiment, a method of operating a counter/timer circuit involves determining a match condition by comparing a count value of the counter/timer circuit with a value stored in a match register of the counter/timer circuit and delaying an assertion of the match condition based on a value programmed in a match companion register of the counter/timer circuit. The match companion register is associated with the match register. Other embodiments are also described.

摘要翻译： 描述了计数器/定时器电路和操作计数器/定时器电路的方法。 在一个实施例中，一种操作计数器/定时器电路的方法包括通过将计数器/定时器电路的计数值与存储在计数器/定时器电路的匹配寄存器中的值进行比较来确定匹配条件，并延迟该匹配的断言 基于在计数器/定时器电路的匹配伴随寄存器中编程的值的条件。 匹配配对寄存器与匹配寄存器相关联。 还描述了其它实施例。

公开(公告)号：US06728892B1

公开(公告)日：2004-04-27

申请号：US09474901

申请日：1999-12-30

申请人： William J. Silvkoff ,  Hartmut Habben ,  Neil E. Birns

发明人： William J. Silvkoff ,  Hartmut Habben ,  Neil E. Birns

IPC分类号： G06F126

CPC分类号： H04L12/46 ,  G06F1/3209 ,  G06F1/3287 ,  G06F15/78 ,  H04L1/1664 ,  H04L12/40013 ,  H04L12/40039 ,  H04L12/4135 ,  H04L29/06 ,  H04L47/30 ,  H04L47/621 ,  H04L49/90 ,  H04L49/9094 ,  H04L2012/40215 ,  Y02D10/171 ,  Y02D50/20

摘要： A method for conserving power in a CAN microcontroller that includes a processor core and a CAN/CAL module that includes a plurality of sub-blocks that cooperatively function to process incoming CAL/CAN messages, which method includes the steps of placing the processor core in a power-reduction mode of operation (e.g., a sleep or idle mode of operation), placing the CAN/CAL module in a power-reduction mode of operation, and activating the CAN/CAL module to process an incoming CAL/CAN message (e.g., to perform automatic hardware assembly of a multi-frame, fragmented CAL/CAN message), thereby terminating the power-reduction mode of operation thereof, while the processor core is in its power-reduction mode of operation. In a preferred embodiment, the CAN/CAL module automatically assembles incoming, multi-frame, fragmented messages while the processor core remains in its power-reduction mode of operation, and the CAN/CAL module generates a message-complete interrupt in response to completion of assembly of the multi-frame, fragmented message, whereby the terminating step is executed in response to the message-complete interrupt. In another embodiment, the method includes the steps of placing the entire CAN microcontroller, including both the processor core and the CAN/CAL module in a power-down mode of operation, detecting receipt of an incoming message, and activating the CAN/CAL module in response to the detecting step to process the incoming message (e.g., to perform automatic hardware assembly of a multi-frame, fragmented CAL/CAN message), thereby terminating the power-down mode of operation of the CAN/CAL module, without terminating the power-down mode of operation of the processor core.

摘要翻译： 一种用于在CAN微控制器中节省功率的方法，该微控制器包括处理器核和CAN / CAL模块，CAN模块包括协作地用于处理输入的CAL / CAN消息的多个子块，该方法包括以下步骤：将处理器核放置在 功率降低操作模式（例如，睡眠或空闲操作模式），将CAN / CAL模块置于功率降低操作模式，并激活CAN / CAL模块以处理输入的CAL / CAN消息（ 例如，执行多帧分段的CAL / CAN消息的自动硬件组合），从而在处理器核心处于其功率降低操作模式的同时终止其功率降低模式的操作。 在优选实施例中，CAN / CAL模块在处理器核心保持其功率降低操作模式时自动组合进入的多帧分段消息，并且CAN / CAL模块响应于完成而产生消息完成中断 组装多帧分段消息，由此响应于消息完成中断执行终止步骤。 在另一个实施例中，该方法包括以下步骤：将包括处理器核和CAN / CAL模块的整个CAN微控制器放置在掉电操作模式中，检测输入消息的接收，以及激活CAN / CAL模块 响应于处理传入消息的检测步骤（例如，执行多帧，分段CAL / CAN消息的自动硬件组合），从而终止CAN / CAL模块的掉电模式，而不终止 处理器内核的掉电模式运行。

公开(公告)号：US20120236981A1

公开(公告)日：2012-09-20

申请号：US13487642

申请日：2012-06-04

申请人： CRAIG A. MACKENNA ,  NEIL E. BIRNS

发明人： CRAIG A. MACKENNA ,  NEIL E. BIRNS

IPC分类号： G06M3/02

CPC分类号： H03K21/406 ,  H03K21/38

摘要： A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.

公开(公告)号：US6012128A

公开(公告)日：2000-01-04

申请号：US999667

申请日：1997-10-14

申请人： Neil E. Birns ,  Ori K. Mizrahi-Shalom

发明人： Neil E. Birns ,  Ori K. Mizrahi-Shalom

IPC分类号： G06F12/02 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38 ,  G06F12/06

CPC分类号： G06F9/342 ,  G06F12/0623 ,  G06F9/3861

摘要： A microcontroller with a page zero mode where a memory address space is restricted to one page of a multiple page address space to produce improved performance. Address mapping logic and memory segment selection logic limits addresses to the least significant 16 bits of a possible 24 bit address. Different or alternate microcode program controlled instruction sequences with eliminated high order address clock cycles are used in the page zero mode.

摘要翻译： 具有页零模式的微控制器，其中存储器地址空间被限制为多页地址空间的一页以产生改进的性能。 地址映射逻辑和存储器段选择逻辑将地址限制为可能的24位地址的最低有效16位。 在零页模式中使用具有消除的高阶地址时钟周期的不同或替代的微代码程序控制指令序列。

公开(公告)号：US5887189A

公开(公告)日：1999-03-23

申请号：US786513

申请日：1997-01-21

申请人： Neil E. Birns ,  Ori K. Mizrahi-Shalom

发明人： Neil E. Birns ,  Ori K. Mizrahi-Shalom

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F9/32

CPC分类号： G06F9/5016 ,  G06F9/462

摘要： A microcontroller that provides an environment to run processes developed to run on several prior or low end generation machines with the independent register, status and data space needed for execution, that is, the resources of the microcontroller are a superset of the resources of the prior generation machine. The ability to limit one process from accessing the data space of another independent process is provided by data space segmentation controlled by upper order address bits not accessible by the independent processes. The separate workspaces are configured substantially like a workspace of a prior or low end generation machine allowing the microcontroller to perform the tasks of several independent prior or low end generation machines working in concert.

摘要翻译： 微控制器提供了一个环境，用于运行开发为具有执行所需的独立寄存器，状态和数据空间的多个先前或低端生成机器的程序，即微控制器的资源是先前资源的超集 一代机。 通过由独立进程无法访问的高阶地址位控制的数据空间分段来提供限制一个进程访问另一个独立进程的数据空间的能力。 单独的工作空间被配置为基本上类似于先前或低端发电机的工作空间，允许微控制器执行几个独立的在前或低端发电机工作的任务。

公开(公告)号：US08719749B2

公开(公告)日：2014-05-06

申请号：US13563431

申请日：2012-07-31

申请人： Neil E. Birns ,  Craig A. MacKenna

发明人： Neil E. Birns ,  Craig A. MacKenna

IPC分类号： G06F9/455

CPC分类号： G04F1/005 ,  G04F3/06 ,  H03K7/08

摘要： A counter/timer circuit and a method of operating the counter/timer circuit are described. In one embodiment, a method of operating a counter/timer circuit involves determining a match condition by comparing a count value of the counter/timer circuit with a value stored in a match register of the counter/timer circuit and delaying an assertion of the match condition based on a value programmed in a match companion register of the counter/timer circuit. The match companion register is associated with the match register. Other embodiments are also described.

摘要翻译： 描述了计数器/定时器电路和操作计数器/定时器电路的方法。 在一个实施例中，一种操作计数器/定时器电路的方法包括通过将计数器/定时器电路的计数值与存储在计数器/定时器电路的匹配寄存器中的值进行比较来确定匹配条件，并延迟该匹配的断言 基于在计数器/定时器电路的匹配伴随寄存器中编程的值的条件。 匹配配对寄存器与匹配寄存器相关联。 还描述了其它实施例。

公开(公告)号：US08693614B2

公开(公告)日：2014-04-08

申请号：US13487642

申请日：2012-06-04

申请人： Craig A. MacKenna ,  Neil E. Birns

发明人： Craig A. MacKenna ,  Neil E. Birns

IPC分类号： G06M3/00

CPC分类号： H03K21/406 ,  H03K21/38

摘要： A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.

摘要翻译： 使用计数器/定时器电路产生定时输出信号的计数器/定时器电路和方法使用可配置为多个计数器的多个计数器。 计数器由来自计数器/定时器电路的控制逻辑电路的控制信号控制，其中至少一些控制信号取决于由计数器/定时器电路的事件产生模块产生的事件信号。 生成的事件信号基于由与计数器相关联的状态值限定的输入信号，输出信号和计数器匹配中的至少一个。

公开(公告)号：US08229056B2

公开(公告)日：2012-07-24

申请号：US12972392

申请日：2010-12-17

申请人： Craig A. MacKenna ,  Neil E. Birns

发明人： Craig A. MacKenna ,  Neil E. Birns

IPC分类号： G06M3/02

CPC分类号： H03K21/406 ,  H03K21/38

摘要： A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.

摘要翻译： 使用计数器/定时器电路产生定时输出信号的计数器/定时器电路和方法使用可配置为多个计数器的多个计数器。 计数器由来自计数器/定时器电路的控制逻辑电路的控制信号控制，其中至少一些控制信号取决于由计数器/定时器电路的事件产生模块产生的事件信号。 生成的事件信号基于由与计数器相关联的状态值限定的输入信号，输出信号和计数器匹配中的至少一个。

公开(公告)号：US20120155603A1

公开(公告)日：2012-06-21

申请号：US12972392

申请日：2010-12-17

申请人： CRAIG A. MACKENNA ,  NEIL E. BIRNS

发明人： CRAIG A. MACKENNA ,  NEIL E. BIRNS

IPC分类号： H03K21/00

CPC分类号： H03K21/406 ,  H03K21/38

摘要： A counter/timer circuit and method of generating timed output signals using the counter/timer circuit, uses multiple counters that are configurable to operate as one or more counters. The counters are controlled by control signals from a control logic circuitry of the counter/timer circuit, where at least some of the control signals are dependent on event signals generated by an event generation module of the counter/timer circuit. The generated event signals are based on at least one of: an input signal, an output signal, and a counter match, qualified by a state value associated with the counters.

摘要翻译： 使用计数器/定时器电路产生定时输出信号的计数器/定时器电路和方法使用可配置为多个计数器的多个计数器。 计数器由来自计数器/定时器电路的控制逻辑电路的控制信号控制，其中至少一些控制信号取决于由计数器/定时器电路的事件产生模块产生的事件信号。 生成的事件信号基于由与计数器相关联的状态值限定的输入信号，输出信号和计数器匹配中的至少一个。

公开(公告)号：US06631431B1

公开(公告)日：2003-10-07

申请号：US09474903

申请日：1999-12-30

申请人： William J. Silvkoff ,  Neil E. Birns ,  Peter Hank ,  Mathius Muth

发明人： William J. Silvkoff ,  Neil E. Birns ,  Peter Hank ,  Mathius Muth

IPC分类号： G06F1300

CPC分类号： H04L29/06 ,  G06F13/385 ,  G06F15/78 ,  H04L1/1664 ,  H04L12/4135 ,  H04L47/10 ,  H04L47/30 ,  H04L47/621 ,  H04L49/90 ,  H04L2001/0094 ,  H04L2012/40215

摘要： A method for use in a CAN device (e.g., a CAN microcontroller) that includes a processor core and hardware external to the processor core (e.g., a DMA engine) that writes message data into a designated message buffer for ensuring integrity of the message data stored in the designated message buffer. The method includes providing a three-state semaphore to indicate a current access status of the designated message buffer, the three-state semaphore having a first state indicative of the hardware external to the processor core starting to write new message data into the designated message buffer, a second state indicative of the hardware external to the processor core having finished writing the new message data into the designated message buffer, and, a third state indicative of the processor core starting to read message data from the designated message buffer. The processor core determines whether the designated message buffer is ready to be accessed based on the current state of the semaphore. The processor core, after determining that the designated message buffer is ready to be accessed, reads the message data from the designated message buffer. After the processor core has finished reading the message data from the designated message buffer, it checks the current state of the semaphore to determine whether it has changed to a different state during the time that the processor core was reading the message data from the designated message buffer. If the processor core determines that the current state of the semaphore changed during the time that the processor core was reading the message data from the designated message buffer, it again determines whether the designated message buffer is ready to be accessed, based on the current state of the semaphore. After again determining that the designated message buffer is ready to be accessed, the processor core again reads the message data from the designated message buffer.