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公开(公告)号：US20090161429A1
公开(公告)日：2009-06-25
申请号：US11963245
申请日：2007-12-21
CPC分类号： G11C29/824 , G11C29/82 , G11C2216/30
摘要： A dynamic column redundancy replacement system for programming and reading a non-volatile memory system includes an input data replacement logic block and an output data replacement logic block. A column redundancy match logic block compares a user address to latched fuse addresses of bad columns and identifies address matches to facilitate the replacement of bits from defective memory cells with replacement redundancy bits. For a program mode of operation, a multi-bit data program redundancy register stores actual redundant input data information and a FIFO register masks internal operations of the memory controller logic while a user is sending data. For a read mode of operation, actual redundant output information is stored in a multi-bit data read redundancy register such that, if a match is found, data from the shift register is replaced with redundant data bits and sent to the data output terminal to provide dynamic replacement of data bits from defective non-volatile memory cells.
摘要翻译： 用于编程和读取非易失性存储器系统的动态列冗余替换系统包括输入数据替换逻辑块和输出数据替换逻辑块。 列冗余匹配逻辑块将用户地址与错误列的锁存熔丝地址进行比较，并且识别地址匹配以便于利用替换冗余位替换来自有缺陷的存储器单元的位。 对于程序操作模式，多位数据程序冗余寄存器存储实际的冗余输入数据信息和FIFO寄存器屏蔽用户发送数据时存储器控制器逻辑的内部操作。 对于读取操作模式，实际的冗余输出信息被存储在多位数据读冗余寄存器中，使得如果发现匹配，则来自移位寄存器的数据被替换为冗余数据位，并被发送到数据输出端 提供动态替换有缺陷的非易失性存储单元的数据位。
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公开(公告)号：US20090086541A1
公开(公告)日：2009-04-02
申请号：US11862436
申请日：2007-09-27
IPC分类号： G11C16/06
CPC分类号： G11C29/848 , G11C16/04 , G11C29/789 , G11C2229/726
摘要： A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array. Column redundancy replacement logic, in response to a match output, dynamically substitutes correct data associated with a defective non-volatile memory cell into an I/O program or read data bit stream of the non-volatile memory chip.
摘要翻译： 用于非易失性存储器的列冗余系统包括单独的伴随控制器芯片，其包括用于存储有缺陷的非易失性存储器单元的地址的列冗余RAM存储器阵列。 列冗余匹配逻辑提供对应于非易失性存储器的特定用户输入地址与有缺陷的非易失性存储器单元的地址的匹配的匹配输出信号，存储在列冗余RAM存储器阵列中的所述地址的收集 。 列冗余替换逻辑响应于匹配输出，动态地将与有缺陷的非易失性存储器单元相关联的正确数据替换为非易失性存储器芯片的I / O程序或读取数据位流。
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3.发明授权公开(公告)号：US07515469B1
公开(公告)日：2009-04-07
申请号：US11862436
申请日：2007-09-27
CPC分类号： G11C29/848 , G11C16/04 , G11C29/789 , G11C2229/726
摘要： A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array. Column redundancy replacement logic, in response to a match output, dynamically substitutes correct data associated with a defective non-volatile memory cell into an I/O program or read data bit stream of the non-volatile memory chip.
摘要翻译： 用于非易失性存储器的列冗余系统包括单独的伴随控制器芯片，其包括用于存储有缺陷的非易失性存储器单元的地址的列冗余RAM存储器阵列。 列冗余匹配逻辑提供对应于非易失性存储器的特定用户输入地址与有缺陷的非易失性存储器单元的地址的匹配的匹配输出信号，存储在列冗余RAM存储器阵列中的所述地址的收集 。 列冗余替换逻辑响应于匹配输出，动态地将与有缺陷的非易失性存储器单元相关联的正确数据替换为非易失性存储器芯片的I / O程序或读取数据位流。
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公开(公告)号：US08190950B2
公开(公告)日：2012-05-29
申请号：US11963245
申请日：2007-12-21
CPC分类号： G11C29/824 , G11C29/82 , G11C2216/30
摘要： A dynamic column redundancy replacement system for programming and reading a non-volatile memory system includes an input data replacement logic block and an output data replacement logic block. A column redundancy match logic block compares a user address to latched fuse addresses of bad columns and identifies address matches to facilitate the replacement of bits from defective memory cells with replacement redundancy bits.
摘要翻译： 用于编程和读取非易失性存储器系统的动态列冗余替换系统包括输入数据替换逻辑块和输出数据替换逻辑块。 列冗余匹配逻辑块将用户地址与错误列的锁存熔丝地址进行比较，并且识别地址匹配以便于利用替换冗余位替换来自有缺陷的存储器单元的位。
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